JPH027708A - Automatic gain control circuit - Google Patents

Automatic gain control circuit

Info

Publication number
JPH027708A
JPH027708A JP15695588A JP15695588A JPH027708A JP H027708 A JPH027708 A JP H027708A JP 15695588 A JP15695588 A JP 15695588A JP 15695588 A JP15695588 A JP 15695588A JP H027708 A JPH027708 A JP H027708A
Authority
JP
Japan
Prior art keywords
signal
gain
input
output
detector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15695588A
Other languages
Japanese (ja)
Inventor
Masaru Kunugi
賢 功刀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15695588A priority Critical patent/JPH027708A/en
Publication of JPH027708A publication Critical patent/JPH027708A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To control the gain instantly with respect to a change in input and output signal levels by controlling the gain of an amplifier depending on a detection output of an input signal level detector and a detection output of an output signal level detector. CONSTITUTION:Part of the signal entering an input terminal 1 is extracted by a directional coupler 3a and detected by a detector 4a. Moreover, part of the signal amplified by a Dual-Gate FET AMP 2 is extracted by a directional coupler 3b and detected by a detector 4b. Two signals being detected outputs detected by the detectors 4a, 4b are amplified into a signal of a required level by a differential amplifier 7, the result is fed to the 2nd gate of the AMP 2 thereby controlling the operating state of the AMP 2 and the gain. Thus, the gain is controlled instantly against the input level fluctuation and the gain is accurately controlled against the output level fluctuation.

Description

【発明の詳細な説明】[Detailed description of the invention] 【産業上の利用分野】[Industrial application field]

この発明は、利得を自動的に制御する増幅器の自動利得
制御回路に関するものである。
The present invention relates to an automatic gain control circuit for an amplifier that automatically controls the gain.

【従来の技術】[Conventional technology]

第3図は例えば「マイクロウェーブジャーナルJ (M
icrowave Journal) 1987.9月
、 P2O5に掲載された従来の自動利得制御回路を示
す接続図であり、図において、1は入力端子、2はこの
入力端子1より入力する信号を増幅するデュアルゲート
(Dual−Gate)  F ET  AMP  (
Dual−GateF ETAMPという)、3は出力
レベルの一部を取り出す方向性結合器、4はこの方向性
結合器3より取り出された信号を検波する検波器、5は
検波器4の検波出力を増幅するビデオアンプ、6は出力
端子である。 次に動作について説明する。入力端子1に入った信号は
Dual−Gate F E T A M P 2にて
増幅される。この増幅された信号の一部を方向性結合器
3にて取り出し、この信号を検波器4にて検波する。こ
の検波された信号は、ビデオアンプ5にて所要の大きさ
の信号に増幅され、Dual−Gate F ETAM
P2の第2ゲートに加えられ、Dual−GateF 
E T AM P 2の動作状態を制御し、利得を制御
する。 入力端子1に入力される信号のレベルが変化しても、D
ual−GateF E T AM P 2の動作状態
を変化させ利得を制御することにより出力端子6に出力
される信号レベルを常に一定に保っている。
Figure 3 shows, for example, "Microwave Journal J (M
This is a connection diagram showing a conventional automatic gain control circuit published in P2O5, September 1987. In the diagram, 1 is an input terminal, and 2 is a dual gate (2) that amplifies the signal input from input terminal 1. Dual-Gate) FET AMP (
Dual-GateF ETAMP), 3 is a directional coupler that extracts a part of the output level, 4 is a detector that detects the signal extracted from this directional coupler 3, and 5 is amplified the detection output of the detector 4. 6 is an output terminal. Next, the operation will be explained. The signal input to the input terminal 1 is amplified by the Dual-Gate FET AMP 2. A part of this amplified signal is taken out by a directional coupler 3, and this signal is detected by a detector 4. This detected signal is amplified to a signal of a required size by the video amplifier 5, and the Dual-Gate F ETAM
Added to the second gate of P2, Dual-GateF
Controls the operating state of E T A P 2 and controls the gain. Even if the level of the signal input to input terminal 1 changes, D
By changing the operating state of the ual-GateFETAMP 2 and controlling the gain, the signal level output to the output terminal 6 is always kept constant.

【発明が)1¥決しようとする課題】 従来の自動利得制御回路は以上のように構成されている
ので、入力レベルが変動してから、出力レベルを怒知し
、利得を制御するまで時間がかかり、又、出力レベル変
動に対し、性格に利得を制御するのが困難であるなどの
問題点があった。 この発明は上記のような問題点を解消するためになされ
たもので、入力レベル変動に対して即座に利得が制御で
きるとともに、出力レベル変動に対して、正確に利得を
制御することができる自動利得制御回路を得ることを目
的とする。
[Problem to be solved by the invention] Since the conventional automatic gain control circuit is configured as described above, it takes a long time from when the input level fluctuates to when the output level is notified and the gain is controlled. There are also problems in that it is difficult to precisely control the gain in response to fluctuations in the output level. This invention was made in order to solve the above-mentioned problems, and it is an automatic system that can instantly control the gain in response to input level fluctuations, as well as accurately control the gain in response to output level fluctuations. The purpose is to obtain a gain control circuit.

【課題を解決するための手段】[Means to solve the problem]

この発明に係る自動利得制御回路は、入力信号レベルを
検波する検波器と、出力信号レベルを検波する検波器の
2つの検波出力を差動増幅器の入力として、この差動増
幅器の出力を制御信号としたものである。
The automatic gain control circuit according to the present invention uses two detection outputs of a detector for detecting an input signal level and a detector for detecting an output signal level as inputs of a differential amplifier, and uses the output of the differential amplifier as a control signal. That is.

【作用】[Effect]

この発明における入力信号レベルを検波する検波器と、
出力信号レベルを検波する検波器の2つの出力信号を入
力信号とする差動増幅器は、入力レベル変動に対し即座
に利得を制御するとともに、出力レベル変動に対して、
正確に利得を制御することができる。
A detector for detecting an input signal level in the present invention,
A differential amplifier that uses the two output signals of a detector that detects the output signal level as input signals immediately controls the gain in response to input level fluctuations, and also controls the gain in response to output level fluctuations.
Gain can be precisely controlled.

【実施例】【Example】

以下、この発明の一実施例を図について説明する。第1
図において、1は入力端子、2はこの入力端子lより入
力する信号を増幅する増幅器としてのDual−Gat
eF ET AMP、 3 aは入力レベルの一部を取
り出す方向性結合器、3bはDual−GateF E
T AMP 2の出力レベルの一部を取り出す方向性結
合器、4aは方向性結合器3aより取り出された信号を
検波する検波器、4bは方向性結合器3bより取り出さ
れた信号を検波する検波器、6は出力端子、7は検波器
4aの入力信号の検波出力と検波器4bの出力信号の検
波出力の2信号を入力信号として、Dual−Gate
 F E T AMP2を制御する為に差動増幅する差
動増幅器である。 次に動作について説明する。入力端子1に入った信号は
、Dual−Gate F E T A M P 2に
て増幅される。この入力端子1に入った信号の一部を方
向性結合器3aにて取り出し、この信号を検波器4aに
て検波する。また、Dual−GateF ET AM
P2にて増幅された信号の一部を方向性結合器3bにて
取り出し、この信号を検波器4bにて検波する。検波器
4aにて検波された検波出力と検波器4bにて検波され
た検波出力の2つの信号が、差動増幅器7に入力され、
次いでこの差動増幅器7にて所要の大きさの信号に増幅
されて、Dual−GateF E T AM P 2
の第2ゲートに加えられる。 その結果、口ual−GateF E T AM P 
2動作状態を制御し、利得を制御する。 即ち、入力端子1に入力される信号レベルが変化した場
合、検波器4aの検波出力が変化し、その変化分は差動
増幅器7に加えられ、該差動増幅器7にて所要の制御信
号が作り出され、Dual−GateF E T AM
 P 2の第2ゲートに加えられてDual−Gate
 F E T A M P 2の動作状態を変化させ、
利得を制御することにより、出力端子6に出力される信
号レベルを一定に保つ。 また、温度変動等により、Dual−Gate F E
 TAMP2の利得が変化した際には、検波器4bの検
波出力が変化し、その変化分が差動増幅器7に加えられ
る。そのため差動増幅器7にて所要の制御信号が作り出
され、Dual−Gate F E T A M P2
のゲートに加えられ、Dual−GateF ET A
MP2の動作状態を変化させ、利得を制御することによ
り、出力端子6に出力される信号レベルを一定に保つ。 なお、上記実施例ではDual−Gate F E T
 A MB2にて利得を制御するものを示したが、第2
図に示す様に、入出力側にそれぞれアンプ8a、8bが
あり、該アンプ8a、8bの中間にバリアプルアッテネ
ータ9がある場合でも、バリアプルアッテネータ9の減
衰量を制御することにより全体の利得を制御するので、
上記実施例と同様の効果を奏する。 また、上記実施例では、Dual−Gate F E 
T AMP2が1つの場合を示したが、第2図のバリア
プルアッテネータ9の代わりにDual−Gate F
 E TAMP2を用いた場合の様に、複数個のアンプ
を用いた場合に対しても上記実施例と同様の効果を奏す
る。
An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is an input terminal, and 2 is a Dual-Gat amplifier that amplifies the signal input from this input terminal l.
eFET AMP, 3a is a directional coupler that takes out a part of the input level, 3b is a Dual-GateFET
A directional coupler that takes out a part of the output level of T AMP 2, 4a a detector that detects the signal taken out from the directional coupler 3a, and 4b a detector that detects the signal taken out from the directional coupler 3b. 6 is an output terminal, 7 is a Dual-Gate with two signals, the detection output of the input signal of the detector 4a and the detection output of the output signal of the detector 4b, as input signals.
This is a differential amplifier that performs differential amplification to control FET AMP2. Next, the operation will be explained. The signal input to the input terminal 1 is amplified by the Dual-Gate FET AMP 2. A part of the signal that has entered this input terminal 1 is taken out by a directional coupler 3a, and this signal is detected by a detector 4a. Also, Dual-Gate FET AM
A part of the signal amplified by P2 is taken out by a directional coupler 3b, and this signal is detected by a detector 4b. Two signals, the detection output detected by the detector 4a and the detection output detected by the detector 4b, are input to the differential amplifier 7,
Next, the differential amplifier 7 amplifies the signal to a required magnitude, and the signal is output to the Dual-Gate FET AM P2.
is added to the second gate of As a result, the mouthual-GateFET AM P
2 to control the operating state and control the gain. That is, when the signal level input to the input terminal 1 changes, the detection output of the detector 4a changes, the change is added to the differential amplifier 7, and the differential amplifier 7 outputs the required control signal. Created, Dual-Gate FET AM
Dual-Gate added to the second gate of P2
Changing the operating state of FET A M P 2,
By controlling the gain, the signal level output to the output terminal 6 is kept constant. Also, due to temperature fluctuations, Dual-Gate F E
When the gain of TAMP2 changes, the detection output of the detector 4b changes, and the amount of the change is added to the differential amplifier 7. Therefore, a required control signal is generated in the differential amplifier 7, and the Dual-Gate FETAM P2
Dual-Gate FET A
By changing the operating state of MP2 and controlling the gain, the signal level output to the output terminal 6 is kept constant. In addition, in the above embodiment, Dual-Gate FET
A MB2 showed how to control the gain, but the second
As shown in the figure, even if there are amplifiers 8a and 8b on the input and output sides, and a barrier pull attenuator 9 is located between the amplifiers 8a and 8b, the overall gain can be improved by controlling the amount of attenuation of the barrier pull attenuator 9. Since we control
The same effects as in the above embodiment are achieved. Further, in the above embodiment, Dual-Gate F E
Although the case where there is one TAMP2 is shown, a Dual-Gate F instead of the barrier pull attenuator 9 in FIG.
Even when a plurality of amplifiers are used, such as when E TAMP2 is used, the same effects as in the above embodiment can be obtained.

【発明の効果】【Effect of the invention】

以上のように、この発明によれば、入力信号レベルを検
波する検波器の検波出力と、出力信号レベルを検波する
検波器の検波出力の2つの信号から、差動増幅器にて、
増幅器の利得を制御する制御信号を発生すうことにより
、入力側、出力側の信号レベルの変化に対し、精密に即
座に利得が制御できる効果がある。
As described above, according to the present invention, the differential amplifier uses two signals, the detection output of the detector that detects the input signal level and the detection output of the detector that detects the output signal level.
By generating a control signal to control the gain of the amplifier, the gain can be accurately and instantly controlled in response to changes in signal levels on the input and output sides.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による自動利得制御回路を
示す回路図、第2図はこの発明の他の実施例を示す回路
図、第3図は従来の自動利得制御回路を示す回路図であ
る。 2はDual−GateF ET AMP (増幅器)
、4a、4bは検波器、7は差動増幅器、8a、8bは
アンプ(増幅器)。 なお、図中、同一符号は同一、又は相当部分を2 : 
DuJ−Gite FET AMP (”4’jS!’
)7 蓑?+4=!さ 第 図 第3図 示す。 8a、8b 7)ブ(+′四輻者ぎ)
Fig. 1 is a circuit diagram showing an automatic gain control circuit according to one embodiment of the present invention, Fig. 2 is a circuit diagram showing another embodiment of the invention, and Fig. 3 is a circuit diagram showing a conventional automatic gain control circuit. It is. 2 is Dual-GateFET AMP (amplifier)
, 4a and 4b are detectors, 7 is a differential amplifier, and 8a and 8b are amplifiers. In addition, in the figures, the same reference numerals refer to the same or equivalent parts.
DuJ-Gite FET AMP ("4'jS!'
)7 Mino? +4=! Figure 3 shows this. 8a, 8b 7) Bu (+'shitsushagi)

Claims (1)

【特許請求の範囲】[Claims] 利得を自動的に制御する増幅器の自動利得制御回路にお
いて、入力信号レベルを検波する検波器と、出力信号レ
ベルを検波する検波器と、上記2つの検波器の検波出力
を入力として制御信号を発生する差動増幅器とを備えた
ことを特徴とする自動利得制御回路。
In an automatic gain control circuit for an amplifier that automatically controls the gain, a detector detects the input signal level, a detector detects the output signal level, and the detection outputs of the two detectors are used as input to generate a control signal. An automatic gain control circuit characterized by comprising a differential amplifier.
JP15695588A 1988-06-27 1988-06-27 Automatic gain control circuit Pending JPH027708A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15695588A JPH027708A (en) 1988-06-27 1988-06-27 Automatic gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15695588A JPH027708A (en) 1988-06-27 1988-06-27 Automatic gain control circuit

Publications (1)

Publication Number Publication Date
JPH027708A true JPH027708A (en) 1990-01-11

Family

ID=15638980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15695588A Pending JPH027708A (en) 1988-06-27 1988-06-27 Automatic gain control circuit

Country Status (1)

Country Link
JP (1) JPH027708A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06237197A (en) * 1993-02-09 1994-08-23 Nec Corp Space diversity reception system
JPH06244645A (en) * 1993-02-17 1994-09-02 Nec Corp Amplifier circuit
WO1994029953A1 (en) * 1993-06-03 1994-12-22 Qualcomm Incorporated Temperature compensated variable gain amplifier
JPH0779125A (en) * 1993-06-30 1995-03-20 Alcatel Nv Bias control system of amplifier
US5973560A (en) * 1998-04-16 1999-10-26 Lg Semicon Co., Ltd. Automatic gain control circuit using multiplier and negative feedback system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06237197A (en) * 1993-02-09 1994-08-23 Nec Corp Space diversity reception system
JPH06244645A (en) * 1993-02-17 1994-09-02 Nec Corp Amplifier circuit
WO1994029953A1 (en) * 1993-06-03 1994-12-22 Qualcomm Incorporated Temperature compensated variable gain amplifier
JPH0779125A (en) * 1993-06-30 1995-03-20 Alcatel Nv Bias control system of amplifier
US5973560A (en) * 1998-04-16 1999-10-26 Lg Semicon Co., Ltd. Automatic gain control circuit using multiplier and negative feedback system

Similar Documents

Publication Publication Date Title
EP0377948A3 (en) An optical amplifying device
US5329244A (en) Linear compensating circuit
JPH027708A (en) Automatic gain control circuit
KR920005466A (en) Servo circuit
KR830009689A (en) Signal level control circuit
JP2002043876A (en) Agc circuit
JPH11283151A (en) Fpu device
EP1455446B1 (en) Sensor signal output circuit
KR0151414B1 (en) Automatic gain control circuit of image processing system
US3408575A (en) Receiving apparatus using hall effect feedback control
JPH05343994A (en) Analog signal level conversion circuit
JPS5892149A (en) Detecting circuit for input electric field
JPH0255978A (en) Monopulse receiver
JPH06244645A (en) Amplifier circuit
EP0527029B1 (en) Power control circuit and a method of controlling a power amplifier
GB1140593A (en) Electric amplifier
JPH03115803A (en) Light beam position detector
JPH04156708A (en) Automatic gain control amplifier
JPH03273705A (en) Booster power amplifier
JPH046257Y2 (en)
KR940022521A (en) Servo control method and servo device
JP2919175B2 (en) Linear compensation circuit
JP2590914B2 (en) Distortion generation circuit
JPH03232304A (en) Amplifying circuit
JP2001024453A (en) Automatic gain variable type amplifier system