JPH027491B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a latching relay drive circuit that maintains the current relay operating state even if the input of a control signal is cut off after operation.

It is already known to use latching relays of this type to eliminate the need for a control signal, ie a continuous current to the coil, to sustain the operation of the relay.

For example, the utility model application announcement issued by the Japan Patent Office
There are Publication No. 48702 of 1977 (hereinafter referred to as the first prior art) and Specification of Patent No. 1279777 issued by the Federal Republic of Germany (hereinafter referred to as the second prior art).

These connect a capacitor and a latching relay in series with a current voltage of 100V or 200V, and when a switch is turned on, a one-way current flows through the latching relay to operate the relay, and after a certain period of time, the capacitor is charged to stop the current. The latching relay then mechanically maintains its current state. Then, when the switch is turned off, the capacitor discharges, and the discharge current flows as a reverse current to the latching relay through a semiconductor switching circuit such as a transistor, causing the latching relay to operate in reverse. There is.

The disadvantage of these is that they use capacitors, which require large capacitors and cannot be integrated into ICs. Furthermore, since the latching relay is small, these capacitors cannot be housed in the latching relay as a driving circuit.

In order to improve the above-mentioned shortcomings, further patent application publication No. 80231 of 1980 issued by the Japan Patent Office (hereinafter referred to as No. 3)
prior art) exists.

This is achieved by a combination of transistors without using a capacitor, but this is also the same as the prior art described above, in which a series transistor drive circuit and a latching relay are connected to a power supply voltage of 100V and 200V. .

By the way, this third prior art cannot be applied to computers. This is, of course,
The same applies to the first and second prior art.

That is, the latching relay is switched at high speed by the output bit of the central processing unit (CPU) and connected to the programmable logic controller (PLC).

So, for example, this CPU has 8 output bits,
The switching speed is as high as 10 μsec. On the other hand, the time required for switching the latching relay, ie, the time required to pass the current through the relay coil, is 100 msec, which is quite different from the above speed.

Therefore, in the third prior art, the latching relay cannot keep up with such high-speed switching, and
There is also no circuitry to supplement it.

The present invention solves the above-mentioned technical problems, enables the circuit portion related to the latching relay to be integrated into an integrated circuit, and also enables the driving of a latching relay that is capable of responding to high-speed switching signals. The purpose is to provide circuits.

The present invention will be explained in detail with reference to one or two embodiments.

1 to 13, the semiconductor switching circuit 1 is a so-called single-turn type latching relay 2.
including. When an excitation current flows through the relay coil 3 in the directions of arrows 4 and 5, the externally connected relay switch 6 changes its switching mode to correspond to the direction of the excitation current, and continues to switch even after the excitation current stops flowing. Self-maintaining aspects. One terminal of the relay coil 3 is connected to a connection point 80 between the first and second transistors 7 and 8, and the other terminal is connected to a connection point 81 between the third and fourth transistors 9 and 10.

The output from the amplifier circuit 11 is given to the base of the fourth transistor 10, and is also applied to the inverting circuit N.
1 to the base of the first transistor 7. The output from the other amplifier circuit 12 is applied to the base of the second transistor 8 and also to the base of the third transistor 9 via the inverting circuit N2. Outputs from AND gates G1 and G2 are given to amplifier circuits 11 and 12, respectively.

Figure 2 shows the flip-flop 1 shown in Figure 1.
FIG. 3 is a specific electrical circuit diagram of No. 3. A first input signal from the set input terminal S is input to NOR gate G3. A delay circuit 82 consisting of a resistor 14, a capacitor 15, and inverting circuits 16 and 17 is connected in series to the NOR gate G3. The second input signal from the reset input terminal R is connected to the NOR gate G.
4 is input. The switching speed of these first and second input signals is a time value of 10 .mu.sec, which is a high speed switching based on the output bits of the CPU. The output from NOR gate G4 is applied to another delay circuit 83 consisting of resistor 18, capacitor 19 and inverting circuits 20 and 21. These delay circuits 82, 8
3 cuts extremely short noise signals to prevent the latching relay 2 from malfunctioning. Inversion circuit 1
The set output QF, which is the output from 7 or the first control output of flip-flop 13, is
Given to NOR gate G4. Also, inverting circuit 2
The output from the flip-flop 13, ie, the reset output F, which is the opposite control output from the flip-flop 13, is input to the NOR gate G3. A signal from circuit 22 for performing a toggle operation is applied to NOR gates G3 and G4. Toggle input terminal T
The signal from is inverted by inverting circuit 23, the inverted output of which is shown in FIG. The output of this inverting circuit 23 is applied to one input of a NAND gate 27 via an inverting circuit 24, a resistor 25, and a capacitor 26. The output of the inverting circuit 23 is
It is applied to the other input of NAND gate 27.
The output of capacitor 26 is shown in FIG. The output of NAND gate 27 is shown in FIG. The output of NOR gate G3 is shown in FIG. 3, and the output from inverter circuit 17, ie, the set output QF of flip-flop 13, is shown in FIG. 3. The output of NOR gate G4 is shown in FIG. 3, and the output from inverter circuit 21, ie, the reset output F of flip-flop 13, is shown in FIG. 3. According to such a flip-flop 13, the set output QF and the reset output F are different from each other at times T1 and T1.
The value is the same only between 2. Here, the first and second input signals and other noise signals are also temporally distinguished.

FIG. 4 shows a specific electrical circuit of the pulsing circuit 29. The pulsing circuits 28, 30, and 31 have the same configuration as the pulsing circuit 29. Pulsing circuits 28-31 include resistors 32-36, integral type capacitors 37-41, and inverting circuits 42-4.
5, and the outputs of the integrating capacitors 40 and 41 are input to the NAND gate G6. 5. When the input signal shown in FIG. 1 is applied, the inverting circuits 42 to 45
The outputs shown in FIGS. 5 2 to 5 are obtained respectively. From NAND gate G6,
The output shown in is derived. According to such pulse forming circuits 28 to 31, even when pulses 46 to 48 of less than 30 μsec are input as shown in FIG. 6, the output from the inverting circuit 42 is as shown in FIG. 6, 2. This feature prevents malfunctions caused by noise. Note that in the pulsing circuit 28, an exclusive OR gate is used in place of the NAND gate G6.

The timer 49 includes a flip-flop 50 having, for example, four toggle input terminals T connected in series.
53 and an astable/monostable multivibrator 54 which inputs the periodic signal shown in FIG. 54 performs an oscillation operation. 72 to 75 show waveforms of set outputs Q1 to Q4 of flip-flops 50 to 53.

A power supply voltage is applied to the terminal 55. When the power is turned on, the pulse generated by the differential capacitor 56 and the resistor 57 is transmitted to the flip-flops 50 to 50.
53 to set the reset output 4 to a low level, and is also applied to the reset input terminal R of the flip-flop 13 via the OR gate G15, resetting the flip-flop 13 and setting the set output QF to a high level.
to low level.

A monostable signal is input to the input terminal P1 as shown in Fig. 81.
Assume that the input is as follows. This signal is processed by the Schmitt circuit 58 to prevent malfunctions at its rise and fall.
Further, in order to prevent malfunctions due to low-level noise, the signal is level-discriminated and converted into a pulse by a pulse forming circuit 28.

9 1 and 9 2 show the pulsing circuit 28
shows the inputs and outputs of FIG. 9 shows the output waveform of the NOR gate G7 included in the double operation prohibition circuit 59. A signal having a waveform that is an inversion of the waveform shown in FIG. Therefore, the set output QF of the flip-flop 13 rises as shown in FIG. 9, and the reset output F falls as shown in FIG. 9. Therefore, the output of the NAND gate G10 to which the set output QF and reset output F are input is as shown in FIG. , resets the flip-flops 50 to 53 of the timer 49, and also resets the AND gates G1 and G2.
Prevent the condition from being satisfied. The reset output 4 of the flip-flop 53 becomes high level due to the output of the NAND gate G10, and the timer 49 starts the time-limiting operation. Flip-flop 52, 53
The reset outputs 3, 4 from are shown in FIGS. 9-7 and 9-8. Double operation prohibition circuit 59
These reset outputs Q3 and Q4 are input to the NOR gate G9, and the output of the NOR gate G9 is shown in FIG. NOR gate G
The time T4 during which the output from the timer 49 is at a low level is 1/2 of the time limit T3 of the timer 49 (T4=
T3/2), during this period T4, NAND gate G8
From then on, input of the next toggle signal to the flip-flop 13 is prohibited. Therefore, when adjacent consecutive signals are input to the NOR gate G7, the flip-flop 13 does not change its stable state, and malfunctions due to noise or the like are prevented. The output from reset output 4 of flip-flop 53 is applied to AND gates G1 and G2. After the time limit T3 has elapsed, the output from the AND gate G1 passes through the amplifier circuit 11 to the first and fourth gates.
Transistors 7 and 10 are made conductive. Therefore, an exciting current flows through the relay coil 3 in the direction of the arrow 4. The output from AND gate G1 is shown in FIG. 82. This time limit is the time required for switching the relay coil 3 of the latching relay 2, and was set to 100 msec in the experiment.

At the falling edge of the monostable signal of FIG. 81 applied to the input terminal P1, the pulsing circuit 2
A signal from the flip-flop 8 is input to the toggle input terminal T of the flip-flop 13 via the double operation inhibiting circuit 59. Therefore, the stable state of the flip-flop 13 changes, and the output shown in FIG. 8 is derived from the AND gate G2. Accordingly, the second and third transistors 8 and 9 become conductive, and the excitation current flows through the relay coil 3 in the direction of the arrow 5 for a limited time T3.

The time limit T3 of the timer 49 is selected to be slightly longer than the operating time required for the relay switch 6 of the latching relay 2 to switch.

When a toggle signal is applied to the input terminal 2 as shown in FIG. Thus, AND gate G1,
Outputs are derived from G2 as shown in FIG. 10 2 and FIG. 10 3, respectively. Therefore, the relay switch 6 changes its switching mode each time a toggle signal is input.

When a set signal is applied to the input terminal P3 as shown in FIG.
The flip-flop 13 is set via 4.
A signal shown in FIG. 11 is derived from the AND gate G1 each time the set signal is input. The output of AND gate G2 remains at a low level as shown in FIG. 11.

When a reset signal is input to the input terminal P4 as shown in FIG. 12, the reset signal resets the flip-flop 13 via the Schmitt circuit 62, the pulse generator 31 and the OR gate G15. Therefore, the pulse shown in FIG. 12 is derived from the AND gate G2, and the pulse shown in FIG.
The output of 1 remains at low level as shown in FIG. 12 2.

FIG. 13 shows a semiconductor switching circuit 69 including a so-called two-wound latching relay 68. This switching circuit 69 replaces the switching circuit 1 shown in the first diagram. The latching relay 68 maintains itself by changing the switching mode of an externally connected relay switch 71 when an excitation current flows through one relay coil 70, and when an excitation current flows through the other relay coil 72, the latching relay 68 changes the switching mode of an externally connected relay switch 71. The switching mode changes and it becomes self-maintaining. Transistors 73 and 74 are connected in series to the relay coils 70 and 72, respectively. The bases of these transistors 73 and 74 are connected to amplifier circuits 11 and 12, respectively.
Such a semiconductor switching circuit 69 can also be implemented in conjunction with the present invention. By detecting signals from connection points 75 and 76 between relay coils 70 and 72 and transistors 73 and 74, it is possible to indirectly confirm whether or not latching relay 68 has operated.

Referring again to Figure 1, the regulated output voltage
The output from the constant voltage power supply with Vcc is connected to the resistor 84
and a capacitor 85. The output of capacitor 85 is connected to AND gate G1
1 and the other input of AND gate 11 via an inverting circuit N3 having a level discrimination function. When the power is turned on or when recovering from a momentary power outage, the capacitor 85 is charged and its output voltage increases. The output voltage of the capacitor 85 is applied to the inverting circuit N
If it is less than the discrimination level of 3, AND gate G
A high level signal is derived from 11. As a result, flip-flops 50-53 included in timer 49 are reset. The discrimination level of the inverting circuit N3 is selected to be equal to or higher than the lowest voltage at which the remaining circuit elements shown, which are energized by the output from the constant voltage power supply, can operate normally.

The output from the inverting circuit N3 is the AND gate G1.
2 and G13. The output of the constant voltage power supply is also connected to a resistor 86 and a switch 87.
given to a series circuit consisting of. The output from the connection point 88 between the resistor 86 and the switch 87 is AND
It is applied to the other input of gate G13, and also applied via inverting circuit N to the other input of AND gate G12. The output from AND gate G12 sets flip-flop 13 via OR gate G14. The output from AND gate G13 resets flip-flop 13 via OR gate G15.

When the output voltage of the capacitor 85 is less than the discrimination level of the inverting circuit N3 when the power is turned on or when recovering from a momentary power outage with the switch 87 cut off, a Hano level signal is derived from the AND gate G13. This resets the flip-flop 13. switch 87
When the output voltage of the capacitor 85 is less than the discrimination level of the inverting circuit N3 when the power is turned on or when recovering from a momentary power outage while the capacitor 85 is in a conductive state, a high level signal is derived from the AND gate G12. Flip-flop 13 is set. When the output voltage of the capacitor 85 becomes equal to or higher than the discrimination level of the inverting circuit N3, the outputs of the AND gates G11, G12, and G13 become low level, and the above-mentioned operation can be performed according to the signals from the input terminals P1 to P4. .

As another embodiment of the present invention, the switch 87 is used as a relay switch of the latching relay 2, and when the excitation current flows through the relay coil 3 in the direction of the arrow 4, the switch 87 becomes conductive, and the switch 87 becomes conductive in the direction of the arrow 5 in the opposite direction. The switch 87 may be configured to shut off when the excitation current flows in the direction. As a result, the switching mode of the relay switch 6 of the latching relay 2 is always returned to the reset state even after the power is turned on and after recovery from the momentary power outage, so that the switching mode of the relay switch 6 before the power is turned on and before the instantaneous power outage occurs, and the CPU For example, one latching relay connected in 8 bits is in the set state, and this is an auto-set or reset function to ensure that there is no state different from a predetermined program.

As described above, according to the present invention, the first and second
input signals are responded to by the flip-flop, and alternately provide a first control signal and an inverse control signal as outputs and are applied to a timer circuit for time-limited outputs, such that the first and second input signals are extremely Since the semiconductor switching circuit is kept energized for the operating current time required by the latching relay even if it is for a short time, it is possible to respond to high-speed switching signals and to integrate it into an integrated circuit. It has great technical value in the manufacture of latching relay drive circuits and their application circuits. Moreover, since the power supply voltage of the semiconductor switching circuit is detected and the flip-flop is placed in a predetermined stable state when the power supply voltage is less than a predetermined discrimination level, it is possible to prevent the power supply from being interrupted due to a power failure, for example, during relay operation. It is also possible to keep the relays always in the reset state, thereby preventing only one relay out of many relays from being in the set state.

[Brief explanation of drawings]

Fig. 1 is an electrical circuit diagram of an embodiment of the present invention;
The figure shows a specific electric circuit diagram of the flip-flop 13, FIG. 3 is a waveform diagram for explaining the operation of the flip-flop 13, and FIG. 4 shows the pulse generator 2.
8 to 31 are specific electrical circuit diagrams, FIGS. 5 and 6 are waveform diagrams for explaining the operations of the pulse generators 28 to 31, and FIG. 7 is a waveform diagram for explaining the operation of the timer 49. , FIG. 8 is a waveform diagram for explaining the monostable operation, FIG. 9 is a waveform diagram for explaining the operation of the double operation prohibition circuit 59, and FIG.
The figure is a waveform diagram for explaining the toggle operation.
The figure is a waveform diagram for explaining the set operation.
The figure is a waveform diagram for explaining the reset operation.
FIG. 3 is an electrical circuit diagram of another semiconductor switching circuit 69. 1, 69... Semiconductor switching circuit, 2... Latching relay, 13, 50-53... Flip-flop, 28-31... Pulsing circuit, 49... Timer circuit, 58, 60-62... Schmitt circuit, 59
...Double operation prohibition circuit.

Claims (1)

[Claims] 1 Output a control signal in response to a first input signal, output a control signal opposite to the above in response to a second input signal, and output a control signal from the first input signal to the second input signal. In the latching relay drive circuit, the latching relay maintains the current relay operating state even if the output of the control signal is cut off, the first and second input signals are responded to by a flip-flop, and the flip-flop The flip-flop outputs the first control signal and the reverse control signal alternately depending on the change in the stable state, and the output of the control signal from this flip-flop is drawn into a timer circuit, which controls the latching relay by a time-limited output. A latching relay is required to control a semiconductor switching circuit that drives a circuit for a certain period of time, and this limited output time requires a latching relay even if the first and second input signals are output for a very short time after the timer circuit responds to the control signal. the semiconductor switching circuit is kept energized for an operating current time of A latching relay drive circuit characterized by being equipped with an auto-set and reset circuit that sets a predetermined stable state.