JPH0328011B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a latching relay drive circuit that maintains the current relay operating state even if the input of a control signal is cut off after operation.

It is already known to use latching relays of this type to eliminate the need for a control signal, ie a continuous current to the coil, to sustain the operation of the relay.

For example, the utility model application announcement issued by the Japan Patent Office
There are Publication No. 48702 of 1977 (hereinafter referred to as the first prior art) and Specification of Patent No. 1279777 issued by the Federal Republic of Germany (hereinafter referred to as the second prior art).

These connect a capacitor and a latching relay in series to a power supply voltage of 100V or 200V, and when a switch is turned on, a one-way current flows through the latching relay to operate the relay, and after a certain period of time, the capacitor is charged to stop the current. The latching relay then mechanically maintains its current state. Then, when the switch is turned off, the capacitor discharges, and the discharge current flows as a reverse current to the latching relay through a semiconductor switching circuit such as a transistor, causing the latching relay to operate in reverse. There is.

The disadvantage of these is that they use capacitors, which require large capacitance and cannot be integrated into ICs.
Furthermore, since the latching relay is small, these capacitors cannot be housed in the latching relay as a driving circuit.

In order to improve the above-mentioned shortcomings, further patent application publication No. 80231 of 1980 issued by the Japan Patent Office (hereinafter referred to as No. 3)
prior art) exists.

This is achieved by a combination of transistors without using a capacitor, but this is also the same as the prior art described above, in which a series transistor drive circuit and a latching relay are connected to a power supply voltage of 100, 200V. .

By the way, this third prior art cannot be applied to computers. This is, of course,
The same applies to the first and second prior art.

That is, the latching relay is switched at high speed by the output bits of the central processing unit (CPU) and connected to the programmable logic controller (PLC).

So, for example, this CPU has 8 output bits,
The switching speed is as high as 10 μsec. On the other hand, the time required to switch the latching relay, that is, the time required to run the current through the relay coil is 100 m.
sec is considerably different from the above speed.

Therefore, in the third prior art, the latching relay cannot keep up with such high-speed switching, and
There is also no circuitry to supplement it.

The present invention solves the above-mentioned technical problems and provides a latching relay drive circuit that can integrate circuit parts related to the latching relay and can handle high-speed switching signals. The purpose is to

The present invention will be explained in detail with reference to one or two embodiments.

1 to 13, the semiconductor switching circuit 1 is a so-called single-turn type latching relay 2.
including. When an excitation current flows through the relay coil 3 in the directions of arrows 4 and 5, the externally connected relay switch 6 changes its switching mode to correspond to the direction of the excitation current, and continues to switch even after the excitation current stops flowing. Self-maintaining aspects. One terminal of the relay coil 3 is connected to the connection point between the first and second transistors 7 and 8, and the other terminal is connected to the connection point between the third and fourth transistors 9 and 10.

The output from the amplifier circuit 11 is applied to the base of the fourth transistor 10 and the base of the first transistor 7. The output from the other amplifier circuit 12 is applied to the base of the second transistor 8 and the base of the third transistor 9. Outputs from AND gates G1 and G2 are given to amplifier circuits 11 and 12, respectively.

Figure 2 shows the flip-flop 1 shown in Figure 1.
FIG. 3 is a specific electrical circuit diagram of No. 3. A first input signal from the set input terminal S is input to NOR gate G3. A delay circuit including a resistor 14, a capacitor 15, and inverting circuits 16 and 17 is connected in series to the NOR gate G3. A second input signal from reset input terminals R1 and R2 is input to NOR gate G4. The switching speed of these first and second input signals is a time value of 10 .mu.sec, which is a high speed switching based on the output bits of the CPU. The output from NOR gate R4 is resistor 18, capacitor 1
9 and another delay circuit consisting of inverting circuits 20 and 21. These delay circuits cut out extremely short noise signals to prevent the latching relay 2 from malfunctioning. The output from the inverting circuit 17, ie, the set output QF, which is the first control output of the flip-flop 13, is applied to the NOR gate G4. Further, the output from the inverting circuit 21, that is, the reset output F, which is the reverse control output of the flip-flop 13, is a NOR
It is input to gate G3. NOR gate G3,G
4 is given a signal from a circuit 22 for performing a toggle operation. The signal from the toggle input terminal T is inverted by an inverting circuit 23, the inverted output of which is shown in FIG. The output of this inverting circuit 23 is connected to an inverting circuit 24, a resistor 25 and a capacitor 2.
6 to one input of the NAND gate 27. The output of the inverting circuit 23 is given to the other input of the NAND gate 27. capacitor 2
The output of 6 is shown in FIG. The output of NAND gate 27 is shown in FIG. The output of NOR gate G3 is shown in FIG.
The set output QF of 3 is as shown in FIG. The output of NOR gate G4 is shown in FIG. 3, and the output from inverter circuit 21, ie, the reset output F of flip-flop 13, is shown in FIG. 3. According to the flip-flop 13, the set output QF and reset output F have the same value only during times T1 and T2. Here, the first and second input signals and other noise signals are temporally distinguished.

FIG. 4 shows a specific electrical circuit of the pulsing circuit 29. The pulsing circuits 28, 30, and 31 have the same configuration as the pulsing circuit 29. The pulsing circuits 28-31 include resistors 32-36, integral type capacitors 37-41, and inverting circuits 42-31.
45, and the outputs of the integrating capacitors 40 and 41 are input to the NAND gate G6. 5. When the input signal shown in FIG. 1 is applied, the inverting circuits 42 to 4
5, outputs shown in FIGS. 52 to 5 are obtained, respectively. The output shown in FIG. 5 is derived from the NAND gate G6. According to such pulse forming circuits 28 to 31, even when pulses 46 to 48 of less than 30 μsec are input as shown in FIG. 6, the output from the inverting circuit 42 is as shown in FIG. 6, 2. This feature prevents malfunctions caused by noise. In addition, the pulsing circuit 28
In this case, an exclusive OR gate is used in place of the NAND gate G6.

The timer 49 is connected to a flip-flop 5 having, for example, four toggle input terminals T.
0 to 53, and the 7th flip-flop is 50 on the first stage.
The multivibrator 54 includes a stable multivibrator 54 to which the periodic signal shown in FIG.
72 to 75 are flip-flops 50 to 5.
3 shows the waveforms of the set outputs Q1 to Q4.

A power supply voltage is applied to the terminal 55. When the power is turned on, the pulse generated by the differential capacitor 56 and the resistor 57 is transmitted to the flip-flops 50 to 50.
53 to set the reset output 4 to a low level, and at the same time, it is applied to the reset input R2 of the flip-flop 13.
and set output QF to high level.
Set the reset output F to low level.

A monostable signal is input to the input terminal P1 as shown in Fig. 81.
Assume that the input is as follows. This signal is processed by the Schmitt circuit 58 to prevent malfunctions at its rise and fall.
Further, in order to prevent malfunctions due to low-level noise, the signal is level-discriminated and converted into a pulse by a pulse forming circuit 28.

9 1 and 9 2 show the pulsing circuit 28
shows the inputs and outputs of FIG. 9 shows the output waveform of the NOR gate G7 included in the double operation prohibition circuit 59. A signal having a waveform that is an inversion of the waveform shown in FIG. Therefore, the set output QF of the flip-flop 13 rises as shown in FIG. 9, and the reset output F falls as shown in FIG. 9. Therefore, the output of the NAND gate G10 to which the set output QF and reset output F are input is as shown in FIG. , resets the flip-flops 50 to 53 of the timer 49, and also resets the AND gates G1 and G2.
Prevent the condition from being satisfied. The reset output 4 of the flip-flop 53 becomes high level due to the output of the NAND gate G10, and the timer 49 starts the time-limiting operation. Flip-flop 52, 53
The reset outputs 3, 4 from are shown in FIGS. 9-7 and 9-8. Double operation prohibition circuit 59
These reset outputs Q3 and Q4 are input to the NOR gate G9, and the output of the NOR gate G9 is shown in FIG. NOR gate G
The period T4 during which the output from the timer 49 is at a low level is 1/2 of the time limit T3 of the timer 49 (T4=
T3/2), during this period T4, NAND gate G8
From then on, input of the next toggle signal to the flip-flop 13 is prohibited. Therefore, when adjacent consecutive signals are input to the NOR gate G7, the flip-flop 13 does not change its stable state, and malfunctions due to noise or the like are prevented. The output from reset output 4 of flip-flop 53 is applied to AND gates G1 and G2. After the time limit T3 has elapsed, the output from the AND gate G1 passes through the amplifier circuit 11 to the first and fourth gates.
Transistors 7 and 10 are made conductive. Therefore, an exciting current flows through the relay coil 3 in the direction of the arrow 4. The output from AND gate G1 is shown in FIG. 82. This time limit is the time required to switch the coil 3 of the latching relay 2, and in the experiment
It was set to 100m sec.

At the falling edge of the monostable signal of FIG. 81 applied to the input terminal P1, the pulsing circuit 2
A signal from the flip-flop 8 is input to the toggle input terminal T of the flip-flop 13 via the double operation inhibiting circuit 59. Therefore, the stable state of the flip-flop 13 changes, and the output shown in FIG. 8 is derived from the AND gate G2. Accordingly, the second and third transistors 8 and 9 become conductive, and the excitation current flows through the relay coil 3 in the direction of the arrow 5 for a limited time T3.

The time limit T3 of the timer 49 is selected to be slightly longer than the operating time required for the relay switch 6 of the latching relay 2 to switch.

When a toggle signal is applied to the input terminal P2 as shown in FIG.
and is inputted to the double operation prohibition circuit 59 via the pulse generation circuit 29. Thus, AND gate G1,
Outputs are derived from G2 as shown in FIG. 10 2 and FIG. 10 3, respectively. Therefore, the relay switch 6 changes its switching mode each time a toggle signal is input.

When a set signal is applied to the input terminal P3 as shown in FIG. A signal shown in FIG. 11 is derived from the AND gate G1 each time the set signal is input. AND gate G
The output of No. 2 remains at a low level as shown in FIG. 11.

When a reset signal is input to the input terminal P4 as shown in FIG. Therefore
The pulse of FIG. 12 is derived from the AND gate G2, whereas the output of the AND gate G1 is the first
2 remains at low level as shown in Figure 2.

FIG. 13 shows a semiconductor switching circuit 69 including a so-called two-wound latching relay 68. This switching circuit 69 replaces the switching circuit 1 shown in the first diagram. The latching relay 68 maintains itself by changing the switching mode of an externally connected relay switch 71 when an excitation current flows through one relay coil 70, and when an excitation current flows through the other relay coil 72, the latching relay 68 changes the switching mode of an externally connected relay switch 71. The switching mode changes and it becomes self-maintaining. Transistors 73 and 74 are connected in series to the relay coils 70 and 72, respectively. The bases of these transistors 73 and 74 are connected to amplifier circuits 11 and 12, respectively.
Such a semiconductor switching circuit 69 can also be implemented in conjunction with the present invention. By detecting the signal from the connection point between the relay coils 70, 72 and the transistors 73, 74, it is possible to indirectly confirm whether the latching relay 68 has operated.

As described above, according to the present invention, in the first, second, and third NOR gates G3, G4, and G9, the term "NOR gate" refers to an output waveform similar to that when an input signal is inverted and applied to an OR gate. It is used to mean an OR gate that can obtain .

As described above, according to the present invention, by applying a signal to the toggle input terminal T, an exciting current is caused to flow through the relay coils 3; 70, 72 for a time slightly longer than the operating time of the latching relays 2, 68. This makes it possible to handle high-speed switching signals and to integrate the circuit, which is of great technical value in the manufacture of latching relay drive circuits and application circuits thereof.

Further, according to the present invention, the output of the timer 49 including the oscillation circuit 54 and the counters 50 to 53 and the output of the flip-flop 13 are applied to the AND gates G1 and G2, and these outputs are applied to the semiconductor switching circuit 1.
A single winding latching relay 6 is applied to the input terminal of
9 relay coils 70 and 72 are driven.

Therefore, there is no need to connect a time constant circuit including an external capacitor to determine the time to drive the relay coils 3; 70, 72. This also facilitates integration into circuits.

When driving the single winding latching relay 2,
Since the second and fourth transistors are conductive only when the relay coil 3 is driven, there is no delay in operation due to accumulation time, and the first and second transistors 7 and 8
Also, the third and fourth transistors 9 and 10 do not become conductive at the same time and a large spike current flows.

[Brief explanation of drawings]

Fig. 1 is an electrical circuit diagram of an embodiment of the present invention;
The figure shows a specific electric circuit diagram of the flip-flop 13, FIG. 3 is a waveform diagram for explaining the operation of the flip-flop 13, and FIG. 4 shows the pulse generator 2.
8 to 31 are specific electrical circuit diagrams, FIGS. 5 and 6 are waveform diagrams for explaining the operations of the pulse generators 28 to 31, and FIG. 7 is a waveform diagram for explaining the operation of the timer 49. , FIG. 8 is a waveform diagram for explaining the monostable operation, FIG. 9 is a waveform diagram for explaining the operation of the double operation prohibition circuit 59, and FIG.
The figure is a waveform diagram for explaining the toggle operation.
The figure is a waveform diagram for explaining the set operation.
The figure is a waveform diagram for explaining the reset operation.
FIG. 3 is an electrical circuit diagram of another semiconductor switching circuit 69. 1, 69... Semiconductor switching circuit, 2... Latching relay, 13, 50-53... Flip-flop, 28-31... Pulsing circuit, 49... Timer circuit, 58, 60-62... Schmitt circuit, 59
...Double operation prohibition circuit.

Claims (1)

[Claims] 1. A switching circuit 1, in which a first transistor 7 and a second transistor 8 are connected in series, and a third transistor 9 and a fourth transistor 10 are connected in series, Such a switching circuit 1 and a single-winding latching relay 2, one terminal of which is connected to the connection point between the first transistor 7 and the second transistor 8, and the third
a relay coil 3 whose other terminal is connected to the connection point between the transistor 9 and the fourth transistor 10;
and a relay switch 6 whose switching mode corresponds to the direction of the current flowing through the relay coil 3, such a latching relay 2, and a flip-flop 13 for switching control, which receives an input signal from a toggle input terminal T. is applied to one input terminal of the first NAND gate 27; and the input signal is inverted and delayed by a first time constant circuit including a first resistor 25 and a first capacitor 26. a first NOR gate G3 to which the output of the first NAND gate 27 is applied; a second NOR gate G4 to which the output of the first NAND gate 27 is applied; second time constant circuits 14 and 15 including a second resistor 14 and a second capacitor 15 that delay the output of the first NOR gate G3; and a level of the output of the second time constant circuits 14 and 15. Discriminate and derive the set output QF, and
2NOR gate G4, a third time constant circuit 18, 19 including a third resistor 18 and a third capacitor 19 that delay the output of the second NOR gate G4; a flip-flop 13 for switching control, including circuits 20 and 21 for level-discriminating the outputs of the time constant circuits 18 and 19 of No. 3 to derive the reset output F and supplying it to the first NOR gate G3; and the set output QF. and said reset output F, and derives a start signal when these outputs are both at one logic level; an oscillation circuit 54; and a plurality of counters cascaded to said oscillation circuit 54. The latching relay 2 has counters 50, 51, 52, and 53 including flip-flops, and the operation of the latching relay 2 starts from the time when the start signal from the second NAND gate G10 is applied to the counters 50, 51, 52, and 53. The counter flip-flops 50 and 5 transmit a time-limited signal that continues until a predetermined time slightly longer than the time limit.
The counter flip-flop 5 is derived from the final stage 53 of 1, 52, 53 and is located before the final stage 53.
a timer 49 that derives the outputs of 0, 51, and 52 as a double operation prohibition signal; and a double operation prohibition circuit 59, the input signal of which is applied to one input terminal.
3NAND gate G8; and the third NAND gate G8 in response to the time limit signal from the timer 49 and the dual operation prohibition signal.
A third NOR gate G provides an output to the other input terminal of
9, and when the time limit signal is not derived or the dual operation prohibition signal is not derived, the input signal is switched to a switching control flip-flop 13.
Such a double operation prohibition circuit 59, the set output QF of the switching control flip-flop 13, the time limit signal from the timer 49, and the start signal from the second NAND gate G10 are applied to the toggle input terminal T of the switch. a first AND gate G1 which responds and supplies their AND outputs to the first and fourth transistors 7 and 10; the reset output F of the flip-flop 13 for switching control; the time limit signal from the timer 49; and the second NAND gate G10. a second AND gate G2 responsive to the start signal of the latching relay and providing an AND output thereof to the second and third transistors 8 and 9. 2 First transistor 73 and second transistor 7
4, a first relay coil 70 which is a two-wound latching relay 68 and is connected in series with the first transistor 73, and a second relay coil 70 which is connected in series with the second transistor 74. 2 relay coils 72; and a relay switch 71 which assumes one switching mode depending on the current flowing through the first relay coil 70 and assumes the other switching mode depending on the current flowing through the second relay coil 72.
Such a latching relay 69; a first NAND gate 27 which is a switching control flip-flop 13 and to which an input signal from the toggle input terminal T is given to one input terminal; Circuits 24, 25, and 26 delay the delay by a first time constant circuit including a resistor 25 and a first capacitor 26, and apply the output to the other terminal of the first NAND gate 27; and the output of the first NAND gate 27 is applied. a first NOR gate G3; a second NOR gate G4 to which the output of the first NAND gate 27 is applied; a second resistor 14 and a second capacitor 15 that delay the output of the first NOR gate G3; and the outputs of the second time constant circuits 14 and 15 are level-discriminated and derived as a set output QF.
2NOR gate G4, a third time constant circuit 18, 19 including a third resistor 18 and a third capacitor 19 that delay the output of the second NOR gate G4; a flip-flop 13 for switching control, including circuits 20 and 21 for level-discriminating the outputs of the time constant circuits 18 and 19 of No. 3 to derive the reset output F and supplying it to the first NOR gate G3; and the set output QF. and said reset output F, and derives a start signal when these outputs are both at one logic level; an oscillation circuit 54; and a plurality of NAND gates connected in cascade to said oscillation circuit 54. counters 50, 51, 52, 53 including flip-flops for counters, and from the time when the start signal from the second NAND gate G10 is applied to the counters 50, 51, 52, 53, the latching relay 2 The counter flip-flops 50, 5 generate a time-limited signal that continues until a predetermined time slightly longer than the operating time.
The counter flip-flop 5 is derived from the final stage 53 of 1, 52, 53 and is located before the final stage 53.
a timer 49 that derives the outputs of 0, 51, and 52 as a double operation prohibition signal; and a double operation prohibition circuit 59, the input signal of which is applied to one input terminal.
3NAND gate G8; and the third NAND gate G8 in response to the time limit signal from the timer 49 and the dual operation prohibition signal.
A third NOR gate G provides an output to the other input terminal of
9, and when the time limit signal is not derived or the dual operation prohibition signal is not derived, the input signal is switched to a switching control flip-flop 13.
Such a double operation prohibition circuit 59, the set output QF of the switching control flip-flop 13, the time limit signal from the timer 49, and the start signal from the second NAND gate G10 are applied to the toggle input terminal T of the switch. a first AND gate G1 which responds and supplies their AND output to the first transistor 73; the reset output F of the flip-flop 13 for switching control; the time limit signal from the timer 49; and the start signal from the second NAND gate G10. and a second AND gate G2 which responds to the AND outputs of these signals to the second transistor 74.