JPH027475B2 - - Google Patents

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Publication number
JPH027475B2
JPH027475B2 JP57078856A JP7885682A JPH027475B2 JP H027475 B2 JPH027475 B2 JP H027475B2 JP 57078856 A JP57078856 A JP 57078856A JP 7885682 A JP7885682 A JP 7885682A JP H027475 B2 JPH027475 B2 JP H027475B2
Authority
JP
Japan
Prior art keywords
plating
nickel
transparent conductive
conductive film
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57078856A
Other languages
Japanese (ja)
Other versions
JPS58194083A (en
Inventor
Kaname Myazawa
Yoshihiro Oono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP7885682A priority Critical patent/JPS58194083A/en
Publication of JPS58194083A publication Critical patent/JPS58194083A/en
Publication of JPH027475B2 publication Critical patent/JPH027475B2/ja
Granted legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Manufacturing Of Electric Cables (AREA)

Description

【発明の詳細な説明】 本発明は液晶パネル、エレクトロクロミツクパ
ネル等表示パネル(以下液晶パネルを主体に述べ
る。)の製造方法に関するものであり特に金属配
線された液晶パネルに関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a display panel such as a liquid crystal panel or an electrochromic panel (hereinafter, the liquid crystal panel will be mainly described), and particularly relates to a liquid crystal panel having metal wiring.

液晶パネルには透明導電膜が用いられているが
パターンの微細化にともない抵抗が問題になり必
要とする画素以外は金属配線で抵抗の大きいとこ
ろを補つていこうとする動向がある。特に多重マ
トリクスパネルではパターンピツチ10μ程度が必
要とされるため画素以外は金属配線の必要性が生
ずる。通常このような電極構造は、ガラス上に透
明導電膜を全面形成する工程→これをパターニン
グする工程(画素部とリード部を残して)→全面
にCr―Auを真空蒸着する工程→画素部とリード
部以下のCr―Auをエツチング除去する工程によ
つて得るか、又は全面に透明導電膜を全面に形成
する工程→全面にCr―Auを形成する工程→リー
ド部のCr―Au部を残してCr―Auをエツチングす
る工程→リード部及び画素部を残して透明導電膜
をエツチングする工程によつて得ていた。いずれ
の方法も透明導電膜と金属リード部(Cr―Au)
のパターンあわせが非常に困難、透明導電膜、
Cr,Auとそれぞれ独立してエツチングするエツ
チング液の必要性(アンダーエツチングの問題)、
Cr,Au被覆工程が真空法によるため高価である
等々の欠点を有していた。
Transparent conductive films are used in liquid crystal panels, but as patterns become finer, resistance becomes a problem, and there is a trend to use metal wiring to compensate for areas with high resistance except for necessary pixels. In particular, in a multi-matrix panel, a pattern pitch of about 10 microns is required, which necessitates metal wiring for areas other than pixels. Normally, such an electrode structure is created by forming a transparent conductive film on the entire surface of the glass → patterning it (leaving the pixel area and the lead area) → vacuum-depositing Cr-Au on the entire surface → pixel area and A process of etching away the Cr-Au below the lead part, or a process of forming a transparent conductive film on the entire surface → a process of forming Cr-Au on the entire surface → leaving the Cr-Au part of the lead part. It was obtained by etching the Cr--Au using a process followed by etching the transparent conductive film, leaving the lead portion and pixel portion. Both methods involve a transparent conductive film and a metal lead part (Cr-Au).
It is very difficult to match the pattern of transparent conductive film,
The need for an etching solution that etches Cr and Au independently (under-etching problem);
Since the Cr and Au coating process is performed using a vacuum method, it has drawbacks such as being expensive.

本発明の目的は真空法では不可能な透明導電膜
上のみにメツキする技術を使つて歩留りの良い金
属配線液晶パネルを得ることにある。
An object of the present invention is to obtain a metal wiring liquid crystal panel with a high yield by using a technique of plating only on a transparent conductive film, which is impossible with a vacuum method.

本発明によれば前記方法のようなパターン位置
合せ(透明導電膜と金属リード部)の問題がほと
んどなく(大きなパターンである画素部の合わせ
だけであり多少ずれても実用上問題とならない)、
安価に金属リード付き液晶パネルが得られる。
According to the present invention, there is almost no problem with pattern alignment (transparent conductive film and metal lead part) as in the above method (it only involves alignment of the pixel part, which is a large pattern, so even if there is some misalignment, there is no practical problem).
A liquid crystal panel with metal leads can be obtained at low cost.

本発明に用いられる透明な絶縁基板としてソー
ダガラス、石英ガラス、ホウケイ酸ガラス等の無
機カラス、ポリエステル、エポキシ、酢酸セルロ
ース等のプラスチツクフイルムが考えられる。液
晶のモードによつては片側基板は不透明でも良
く、セラミツク上に本発明の電極構造を構成して
も良い、いかにしても信号電極が本発明の電極構
造を有す。用いられる透明導電膜としては酸化ス
ズ系(酸化スズ又は酸化スズにアンチモン、ホウ
素、フツ素等をドーピングしたもの)でも良いし
酸化インジウム系(酸化インジウム又は酸化スズ
をドープしたもの等)でも良い。これらはCVD
法、真空蒸着法、スパツタ法、イオンプレイテイ
ング法、印刷焼成法、浸漬焼付け法、スプレー
法、パイロゾルCVD法等により得られる。
Possible transparent insulating substrates used in the present invention include inorganic glasses such as soda glass, quartz glass, and borosilicate glass, and plastic films such as polyester, epoxy, and cellulose acetate. Depending on the mode of the liquid crystal, one side of the substrate may be opaque, and the electrode structure of the present invention may be formed on ceramic.In any case, the signal electrode has the electrode structure of the present invention. The transparent conductive film used may be tin oxide based (tin oxide or tin oxide doped with antimony, boron, fluorine, etc.) or indium oxide based (indium oxide or tin oxide doped). These are CVD
method, vacuum evaporation method, sputtering method, ion plating method, print baking method, immersion baking method, spray method, pyrosol CVD method, etc.

これらの透明導電膜は所定のフオト工程を経て
HCl、HCl.Zn、Cr2+/Cr3+レドツクス系等を用
いてエツチングパターニングされる。次に透明電
極上にのみニツケルメツキ又はニツケル合金メツ
キする方法としては、通常のSnCl2→PdCl2
NiPメツキ工程のPdCl2工程後に触媒毒である
Pb、Sbを含んだ溶液に浸漬する。又は一液タイ
プの時はニツケル又はその合金メツキ前に前記触
媒毒に浸漬することにより選択的なメツキが得ら
れる。ニツケルメツキ又はニツケル合金メツキの
膜厚は500Å〜10000Åが適当であり密着性からし
て1000Å〜6000Åが適当である。
These transparent conductive films undergo a prescribed photo process.
Etching patterning is performed using HCl, HCl.Zn, Cr 2+ /Cr 3+ redox system, etc. Next, as a method of nickel plating or nickel alloy plating only on the transparent electrode, the usual SnCl 2 →PdCl 2
PdCl in NiP plating process is catalyst poison after 2 steps
Immerse in a solution containing Pb and Sb. Alternatively, in the case of a one-component type, selective plating can be obtained by immersing the nickel or its alloy in the catalyst poison before plating. The thickness of the nickel plating or nickel alloy plating is suitably 500 Å to 10000 Å, and from the viewpoint of adhesion, 1000 Å to 6000 Å.

ニツケルメツキ又はニツケル合金メツキとして
はNi、Ni―P、Ni―B、Ni―Co―P、Ni―Cr
―P、Ni―Fe―P、Ni―Co―Cr―P等であり主
としてニツケル基リン合金、ニツケル基ホウ素合
金が用いられる。透明導電膜上への密着性からし
てNi―P、Ni―B合金が特に優れる。P、Bの
含有量は1wt%〜20wt%が好ましい。これらを無
電解メツキした後密着性を向上させ、耐摩耗性を
向上させるため常温に1週間以上放置するか50℃
〜500℃で熱処理を行なつても良い。
Nickel plating or nickel alloy plating includes Ni, Ni-P, Ni-B, Ni-Co-P, Ni-Cr.
-P, Ni-Fe-P, Ni-Co-Cr-P, etc., and nickel-based phosphorus alloys and nickel-based boron alloys are mainly used. Ni--P and Ni--B alloys are particularly excellent in terms of adhesion to transparent conductive films. The content of P and B is preferably 1 wt% to 20 wt%. After electroless plating these, in order to improve adhesion and wear resistance, leave them at room temperature for at least one week or at 50°C.
Heat treatment may be performed at ~500°C.

前記ニツケル又はニツケル合金被膜を形成後熱
処理する場合は、下層との密着性等が向上するも
ののその表面に導通性がやや劣る酸化ニツケルが
形成されるが、この酸化ニツケルを除去するため
塩化第二鉄の浴中に浸漬させるようにしてもよ
い。又、前記ニツケル又はニツケル合金被覆のエ
ツチングは例えばエツチング部をレジスト後次の
エツチング液(常温)に30秒程度(被膜厚に応じ
て変動)浸漬して行なう。
When the nickel or nickel alloy film is heat-treated after formation, nickel oxide with slightly poor conductivity is formed on the surface although adhesion with the underlying layer is improved. It may also be immersed in an iron bath. Etching of the nickel or nickel alloy coating is carried out, for example, by immersing the etched portion in the next etching solution (at room temperature) for about 30 seconds (varies depending on the thickness of the coating) after resisting.

エツチング液(容量比) リン酸 35% 硝 酸 35% 酢 酸 5% 硫 酸 5% 以下実施例により本発明を詳細に説明する。 Etching liquid (volume ratio) Phosphoric acid 35% Nitric acid 35% Vinegar acid 5% Sulfuric acid 5% The present invention will be explained in detail below with reference to Examples.

実施例 1 第1図のように上パネル基板の走査電極(鎖
線)に対し下パネル基板に四重マトリクスパネル
用に信号電極である透明導電膜(5%の酸化スズ
をドープした酸化インジウム)をエツチング形成
した。リード部1のピツチは10μ、画素部2のサ
イズは70μである。次に無電解メツキプロセスと
して1液性の増感剤である日立化成社製HS101B
で5分間処理し、触媒毒を含んだ日立化成社製
HS201で10分間処理し、水洗後、カニゼン社製
S68D無電解ニツケルリンメツキ液を用いて60℃
で3分間処理し、透明導電膜上のみに(第2図針
線部)ニツケルリンメツキを4000Å施した。次に
フオト工程を経て画素上のニツケルリンメツキを
第3図のように前述の方法によりエツチング除去
した。A―B間の抵抗測定をしたところ第1図で
は10KΩ、第3図では500Ωであつた。第1図で走
査電極と組み合わせ16行×80桁(5×7ドツト)
1/32dutyで四重マトリクスの液晶パネルを作成し たところ端子から遠い所はON状態でもハーフト
ーンになり表示むらが生じた。しかし同様のパネ
ルを第3図の構成で作成したところ表示むらを生
じなかつた。又前述の従来方法で作成したパネル
は電極の切れ、シヨート、ズレ等の不良が90%で
あつたが、本実施例によつて得たものは30%の不
良(全て10μのリード部1の透明導電膜のエツチ
ング切れ)のみであつた。本実施例によつて得ら
れたニツケルリンメツキ被膜はさらに密着性を向
上させ又耐摩耗性を向上させるためにパターン形
成前又はパターン形成後に80℃〜500℃の熱処理
を施しても良い。
Example 1 As shown in Figure 1, a transparent conductive film (indium oxide doped with 5% tin oxide) which is a signal electrode for a quadruple matrix panel is placed on the lower panel substrate in contrast to the scanning electrode (dashed line) on the upper panel substrate. Formed by etching. The pitch of the lead portion 1 is 10μ, and the size of the pixel portion 2 is 70μ. Next, for the electroless plating process, we used a one-component sensitizer, HS101B manufactured by Hitachi Chemical Co., Ltd.
made by Hitachi Chemical Co., Ltd., which contains catalyst poison.
After treatment with HS201 for 10 minutes and washing with water,
60℃ using S68D electroless nickel phosphor plating solution
was treated for 3 minutes, and 4000 Å of nickel phosphor plating was applied only on the transparent conductive film (the needle line area in Figure 2). Next, after a photo process, the nickel plating on the pixels was removed by etching as shown in FIG. 3 by the method described above. When I measured the resistance between A and B, it was 10KΩ in Figure 1 and 500Ω in Figure 3. In Figure 1, combination with scanning electrodes: 16 rows x 80 digits (5 x 7 dots)
When I created a quadruple matrix liquid crystal panel with a duty of 1/32, areas far from the terminals showed halftones and uneven display even in the ON state. However, when a similar panel was made with the configuration shown in FIG. 3, no display unevenness occurred. Furthermore, 90% of the panels produced by the conventional method described above had defects such as broken electrodes, shorts, and misalignments, but the panels obtained by this example had 30% defects (all of which were caused by the 10μ lead portion 1). There was only an etching break on the transparent conductive film. The nickel phosphor plating film obtained in this example may be subjected to heat treatment at 80°C to 500°C before or after pattern formation in order to further improve adhesion and wear resistance.

実施例 2 実施例1において無電解ニツケルリンメツキで
あるカニゼン社製S′68Dの代わりに無電解ニツケ
ルボロンメツキである上村工業社製ベルニツケル
を用い3500Åメツキした。結果は実施例1と同様
であつた。
Example 2 In Example 1, instead of the electroless nickel plating S'68D manufactured by Kanigen Co., Ltd., electroless nickel boron plating used Belnickel manufactured by Uemura Kogyo Co., Ltd. was used for plating with a thickness of 3500 Å. The results were similar to Example 1.

実施例 3 実施例1において無電解ニツケルリンメツキを
1500Å(カニゼン社製S68D)施し、さらにニツ
ケルボロンメツキ(上村工業社製ベルニツケル)
を2000Å施し積層構造にした。これは透明導電膜
への密着性がニツケルリンメツキ被覆の方がニツ
ケルボロンメツキ被膜より優れているためであ
り、又前者は後者に比し表面硬度が劣るためそれ
ぞれの特徴を生かした使い方である。表面硬度は
液晶を配向させる綿布等によるラビング処理工程
に重要な役割をもつている。このようにして作成
した液晶パネルは実施例1と同様の結果であつ
た。
Example 3 Electroless nickel plating was performed in Example 1.
1500Å (S68D made by Kanizen Co., Ltd.) and nickel boron plating (Belnickel made by Uemura Kogyo Co., Ltd.)
2000Å to create a laminated structure. This is because nickel phosphor plating has better adhesion to transparent conductive films than nickel boron plating, and the former has inferior surface hardness compared to the latter, so each should be used to take advantage of its characteristics. . Surface hardness plays an important role in the rubbing process using cotton cloth or the like to orient liquid crystals. The liquid crystal panel produced in this manner had the same results as in Example 1.

実施例 4 実施例1で酸化インジウム透明導電膜の代わり
にCVD法で作成した酸化スズ(酸化アンチモン
を5wt%ドープしたもの)透明導電膜(膜厚500
Å)を用いた。透明導電膜のエツチングは6N塩
酸酸性のCr2+/Cr3+レドツクス系を用いて行なつ
た。A―B間の抵抗は100KΩであつた。実施例
1と同様に無電解ニツケルリンメツキを施し、同
様のパネルを作成した。第3図のA―B間の抵抗
は750Ωであつた。四重マトリクスパネルの特性
は同様であり効果大であつた。
Example 4 Instead of the indium oxide transparent conductive film in Example 1, a tin oxide (doped with 5 wt% antimony oxide) transparent conductive film (film thickness 500 mm) was prepared by CVD method.
Å) was used. Etching of the transparent conductive film was performed using a 6N hydrochloric acid acidic Cr 2+ /Cr 3+ redox system. The resistance between A and B was 100KΩ. Electroless nickel plating was applied in the same manner as in Example 1 to produce a similar panel. The resistance between A and B in Figure 3 was 750Ω. The characteristics of the quadruple matrix panel were similar and the effect was great.

以上述べたように本発明によれば、透明電極の
リード部のみに均一な膜厚の金属膜を容易な工程
で安価に製造できるとともに、大量生産に適した
製造方法が実現できる。
As described above, according to the present invention, a metal film having a uniform thickness can be manufactured only on the lead portion of a transparent electrode at a low cost through a simple process, and a manufacturing method suitable for mass production can be realized.

特に、透明電極上に、ニツケル合金メツキ被膜
を無電解メツキ法により形成したので、透明電極
の全面にわたり均一な膜厚の被膜が得られる。さ
らに、微細化されたリード部パターンに対しても
同様に均一な被膜が形成される。したがつて、画
素部上に形成された前記被膜のエツチングの際に
も、部分的に被膜が残るということがなく、均一
にエツチングされる。さらに、無電解メツキ被膜
として、ニツケル合金メツキ被膜を用いたので、
透明導電膜との密着性に優れている。
In particular, since the nickel alloy plating film is formed on the transparent electrode by electroless plating, a film with a uniform thickness can be obtained over the entire surface of the transparent electrode. Furthermore, a uniform coating is similarly formed on the miniaturized lead pattern. Therefore, even when the film formed on the pixel portion is etched, the film is not left partially and is etched uniformly. Furthermore, since a nickel alloy plating film was used as the electroless plating film,
Excellent adhesion to transparent conductive film.

本発明により得られたパネルは、a―Nパネ
ル、液晶テレビ、時計、電卓等の表示パネルとし
て応用可能である。
The panels obtained according to the present invention can be applied as display panels for aN panels, liquid crystal televisions, watches, calculators, and the like.

【図面の簡単な説明】[Brief explanation of drawings]

第1図…一般の四重マトリクスパネルの透明導
電膜構造図、第2図…本発明により透明導電膜上
にのみニツケルリンメツキを施した電極構造図、
第3図…本発明により画素部のニツケルリンメツ
キをエツチング除去した信号電極構造図。
Fig. 1...A diagram of the transparent conductive film structure of a general quadruple matrix panel, Fig. 2...A diagram of the electrode structure in which nickel plating is applied only on the transparent conductive film according to the present invention.
FIG. 3: A structural diagram of a signal electrode in which the nickel plating in the pixel area has been removed by etching according to the present invention.

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁基板の一方の全面上に形成された透明導
電膜をパターニングして、複数の画素部およびリ
ード部からなる透明電極を形成する工程と、該透
明電極上にのみ選択的に無電解ニツケル合金メツ
キ被膜を形成する工程と、前記画素部上に形成さ
れた前記無電解ニツケル合金メツキ被膜をエツチ
ングして除去する工程とを具備することを特徴と
する表示パネルの製造方法。
1. A process of patterning a transparent conductive film formed on one entire surface of an insulating substrate to form a transparent electrode consisting of a plurality of pixel parts and lead parts, and selectively applying an electroless nickel alloy only on the transparent electrode. A method for manufacturing a display panel, comprising the steps of forming a plating film and etching and removing the electroless nickel alloy plating film formed on the pixel portion.
JP7885682A 1982-05-10 1982-05-10 Manufacture of display panel Granted JPS58194083A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7885682A JPS58194083A (en) 1982-05-10 1982-05-10 Manufacture of display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7885682A JPS58194083A (en) 1982-05-10 1982-05-10 Manufacture of display panel

Publications (2)

Publication Number Publication Date
JPS58194083A JPS58194083A (en) 1983-11-11
JPH027475B2 true JPH027475B2 (en) 1990-02-19

Family

ID=13673464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7885682A Granted JPS58194083A (en) 1982-05-10 1982-05-10 Manufacture of display panel

Country Status (1)

Country Link
JP (1) JPS58194083A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001047790A (en) 1999-08-17 2001-02-20 Kyowa Electric & Chem Co Ltd Memo implement with electronic calculator

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS556346A (en) * 1978-06-27 1980-01-17 Sharp Kk Electrode pattern and method of forming same
JPS5548935A (en) * 1978-10-03 1980-04-08 Sharp Corp Forming of electrode pattern
JPS5752021A (en) * 1980-09-12 1982-03-27 Citizen Watch Co Ltd Manufacture of liquid crystal display cell

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5938068Y2 (en) * 1980-03-27 1984-10-22 株式会社日立製作所 Pattern structure on the board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS556346A (en) * 1978-06-27 1980-01-17 Sharp Kk Electrode pattern and method of forming same
JPS5548935A (en) * 1978-10-03 1980-04-08 Sharp Corp Forming of electrode pattern
JPS5752021A (en) * 1980-09-12 1982-03-27 Citizen Watch Co Ltd Manufacture of liquid crystal display cell

Also Published As

Publication number Publication date
JPS58194083A (en) 1983-11-11

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