JPH0273469A - Logical simulation system - Google Patents

Abstract

PURPOSE:To reduce the throughput of a control processor and at the same time to improve the simulation speed by providing a comparator adding means and a simulation control means containing a connection means, a state value setting means, and a loading means. CONSTITUTION:A comparison adding means 1 adds the comparators 421 and 422 to a simulation model 41 and produces a simulation model 42. The model 42 is loaded to a simulation hardware 3 via a loading means 23 of a simulation control means 2. At the same time, a connection means 21 of the means 2 secures the connection between one of two inputs of the comparator 421 and the outputs of basic elements 411 and 412 included in the logical processors 32, 33 and 34 of the hardware 3. The output receiver of the means 21 is defined as a control processor 31. Then a state value setting means 22 of the means 2 sets the prescribed state value at the other input of the comparator 421. The output state value is set when the comparison conditions are not satisfied. Thus it is possible to avoid the centralized transfer of the state value to the processor 31 and to reduce the throughput of the processor 31. At the same time, the simulation speed is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a logic simulation method.

[Conventional technology]

A logic simulator that executes logic simulations is composed of a plurality of logic processors that execute simulations in parallel and one control processor that controls these logic processors, as seen in, for example, Japanese Unexamined Patent Publication No. 58-222355. Hardware logic simulators are known.

In such a hardware logic simulator,
Simulation target circuit (simulation model)
Conventionally, control for stopping the simulation when the output state value of a specific basic element in the simulation reaches a predetermined state value has been performed as follows. That is, the above predetermined state value is loaded into the control processor when setting the model for each logical processor, and the state value of the specific basic element obtained by performing simulation in each logical processor is loaded from the logical processor. The propagation values are sequentially propagated to the control processor, the control processor compares the propagation values with preloaded state values, and stops the simulation when the comparison condition is satisfied.

(Problems to be Solved by the Invention) In the conventional logic simulation method described above, it is necessary to provide the output state value of a specific basic element to the control processor in order to determine the simulation stop condition. Therefore, it is necessary to transfer the state value from the logic processor to the control processor.Therefore, it is necessary to transfer the state value from the logic processor to the control processor.Therefore, especially when there are multiple simulation stop conditions, that is, there are multiple pairs of specific basic elements and predetermined state values to be compared. In this case, the amount of communication between the control processor and the logical processor increases and the simulation speed decreases.

In addition to controlling logical processors, the control processor also
kI of the state value for determining the simulation stop condition
Since the i-collection and comparison must also be performed, the logic of the control processor becomes complex, the amount of hardware increases, and the cost increases.

The present invention eliminates these conventional drawbacks,
The purpose is to provide a logic simulation method that can reduce the processing amount of a control processor and increase the speed of simulation.

[Means to solve the problem]

In order to achieve the above object, the present invention consists of a plurality of processors operating in parallel, and when the state value of the output of a specific basic element in the simulation model reaches a predetermined state value, a logical simulation is performed. In the hardware logic simulator for stopping the comparator, the comparator adding means adds a comparator to the simulation model, the loading means loads the simulation model to which the comparator is added into the plurality of processors, and a connecting means for connecting one input to the output of the specific basic element; and a state value setting means for setting the predetermined state value to the other input of the comparator; The state value comparison is performed as part of the simulation operation, and the simulation is stopped in response to the satisfaction of the comparison condition of the comparator.

[Effect]

In the logical simulation method of the present invention, the comparator adding means adds the comparator to the simulation model, the loading means loads the simulation model to which the comparator has been added into the plurality of processors, and the connecting means
The manual input of one of the comparators is connected to the output of a specific basic element, and the state value setting means sets a predetermined state value to the other input of the comparator. During actual simulation, state value comparison by the comparator is performed as part of the simulation operation, and the simulation is stopped in response to the satisfaction of the comparison condition of the comparator.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In the figure, 1 is a comparator adding means that adds a comparator to the simulation model 41 and creates a simulation model 42, and 3 is simulation hardware that executes the simulation. This simulation hardware 3 operates according to an event-driven method.

Further, 2 is a simulation control means for controlling the simulation hardware 3.

The simulation control means 2 includes a connection means 21. which changes the connection information of the simulation model within the simulation hardware 3. Simulation hardware 3
The simulation hardware 3 includes a state value setting means 22 for setting state values in the simulation model within the simulation hardware 3, and a loading means 23 for loading the simulation model, state values, etc. into the simulation hardware 3.

The simulation hardware 3 is a logical processor 32.33.3 that executes multiple simulations in parallel.
4 and the logical processors 32, 33, 34 and the information sent by the loading means 23 to the logical processors 32, 33 and 34.
．． 33.34;
Each logic processor 32, 33, 34 has a memory that holds connection information between basic elements, a memory that holds input state values of basic elements, a memory that holds output state values of basic elements, etc., and a simulation model. are loaded into these memories. Further, the connecting means 21 is connected to the loading means 23.
The state value setting means 22 realizes the connection change by changing the contents of the memory that holds the connection information via the loading means 23, and the state value setting means 22 changes the memory that holds the input state value and the memory that holds the output state value through the loading means 23. Setting the status value is achieved by changing the contents.

The simulation model 41 is composed of various basic elements. And this simulation model 41
For example, when the output state value of a specific basic element 411, 412 among these various basic elements becomes a predetermined state value, or when the output state value of another specific basic element 413 becomes another predetermined state value. It is assumed that the simulation is performed so that execution of the simulation is stopped when a predetermined state value is reached.

In this configuration, first, the comparator addition means 1 adds comparators 421 and 422 to the simulation model 41.
is added, and a simulation model 42 is created. At this point, there is no connection between the input and output of the comparators 421 and 422. The simulation model 42 is loaded into the simulation hardware 3 by the loading means 23 of the simulation control means 2. That is, all the basic elements in the simulation model 42 are loaded separately into the logic processors 32, 33, 34, and the comparators 421, 422 are also loaded. At this time, the comparator 42
1 and comparator 422 are loaded into different logical processors. In this manner, when multiple comparators are added, they are loaded evenly or distributed across multiple logical processors. In the example of FIG. 1, elementary elements 411, 413 are loaded into logic processor 32, elementary element 412 and comparator 422 are loaded into logic processor 33, and comparator 421 is loaded into logic processor 34.

The connection means 21 connects the basic element 41 within the logic processor 32.
1 and the output of the basic element 412 in the logic processor 33 and one input of the comparator 421 in the logic processor 34 are connected. Further, the output light of the comparator 421 is used as the control processor 31.

The state value setting means 22 is a comparator 4 in the logic processor 34.
A predetermined state value is set to the other input of 21.

Further, as the output state value of the comparator 421, the state value when the comparison condition is not satisfied is set. By setting the state value where the comparison condition is not met as the output state value, an event is generated when the comparison condition is met. By doing this, the comparator 421
A specific group of basic elements (i.e. basic elements 411 .
412) and a predetermined state value are connected to the comparator 42.
1 will be compared. In a similar manner, the output state value of the elementary element 413 and another predetermined state value are compared in the comparator 422.

In the process of executing the logic simulation, if the comparison condition of the comparator 421 or the comparator 422 is satisfied, an event occurs, and the event is transmitted to the comparator 421.
, 422 is propagated to the control processor 31. Upon catching the event, the control processor 31 sends a stop command to the logical processors 32, 33, 34. Further, the control processor notifies the simulation control means 2 that the simulation has been stopped. As a result, the execution of the logical simulation is stopped.

With the above-described method, even if there are a plurality of similiation stop conditions, there is no need to concentrate and transfer all state values necessary for determining the stop conditions to only the control B processor.

〔Effect of the invention〕

As explained above, in the logic simulation method of the present invention, a comparator is added to the simulation model, and the state value comparison in the added comparator is performed as part of the simulation operation, thereby transmitting the state to the control processor. Intensive transfer of values can be avoided, and operations such as compiling and comparing state values in the control processor are no longer necessary, making it possible to speed up simulation, simplify the logic of the control processor, and reduce costs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, l...Comparator addition means 2...Simulation control means 21...Connection means 22...Status value setting means 23...Loading means 3...Simulation hardware 31...Control Prosensor 32.33.34...Logic processor 41.42...
・Simulation model 411, 412, 413...
・Basic element 421.422... Comparator

Claims (1)

[Claims] Hardware implementation that is composed of a plurality of processors that operate in parallel and that stops logical simulation when the output state value of a specific basic element in a simulation model reaches a predetermined state value. In the logic simulator, a comparator adding means for adding a comparator into a simulation model; a loading means for loading the simulation model to which the comparator has been added into the plurality of processors; and one input of the comparator and the specified input. and a state value setting means for setting the predetermined state value to the other input of the comparator, the state value comparison in the comparator being simulated. carried out as part of
A logic simulation method characterized in that simulation is stopped in response to satisfaction of a comparison condition of the comparator.