JPH02733B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a complex computer system, and particularly to means for efficiently communicating and controlling computers arranged in parallel.

[Technology background]

Scientific and technological problems include solving problems for each point under given conditions in a system consisting of many points distributed in physical space, where each point has interactions with neighboring points. In many cases, it is necessary to calculate changes in values over time. For example, weather and flood prediction problems are one example. However, since these problems involve an enormous amount of calculation, the processing computers are particularly required to be high-speed.

By the way, a composite computer system in which a large number of computers are arranged in a two-dimensional array and adjacent computers can be connected to each other is suitable for processing such problems, and each point in the physical space described above can be arranged in two dimensions. High-speed processing is made possible by allowing each element computer in the array to operate simultaneously in parallel. However, in conventional composite computer systems of this type, communication between a host computer that controls the whole system and each element computer arranged in a two-dimensional array, and communication between each element computer takes a lot of time. There were certain restrictions on speeding up the overall processing, and there were also technical points that needed to be improved, such as the synchronization control of each element computer.

[Purpose of the invention]

An object of the present invention is to improve communication and synchronization control methods in a complex computer system consisting of a plurality of computers arranged in a two-dimensional array, and to realize a faster and more reliable system.

[Configuration and Examples of the Invention] The configuration of the present invention will be described below based on one example.

(1) Overall configuration of the system FIG. 1 is an overall configuration diagram of a composite computer system in which the present invention is implemented. In the figure, 1 is a PU with 32 processing units PU arranged two-dimensionally in 8 rows and 4 columns.
array, 2 is a control unit, 3 is a host computer, 4 is a digital input/output line DI/O, 5 is a disk pack storage device DP, 6 is a magnetic tape device
MT, 7 and 8 are display terminal devices CRT,
9 is a line printer LP, 10 is a communication control device
COM, 11 is the display device CRT, 12 is the keyboard input device KB, 13 is the printer PR, 1
4 indicates a cassette tape device CMT.

The PU array 1 executes multiple tasks in parallel. Each PU has essentially the same functionality as a single-board microcomputer, as described below. The number of PUs that make up the array is 32.
The number is not limited to 1, and in general, any suitable number can be selected. The PU at row m and column n is (m,
n).

The control unit 2 is a microcomputer that controls the PU array 1 and also performs data communication with the host computer 3 or the input/output devices 7 to 10 via the digital input/output line DI/O.

The host computer 3 is a general-purpose minicomputer, compiles/assembles source programs, and loads the obtained object programs into the control unit 2 and PU. Furthermore, parallel tasks are started, necessary data is transferred to and from the control unit 2, and processing results are output.

(2) Configuration of PU array FIG. 2 is a detailed configuration diagram of one processing unit PU in the m-th row and n-th column in the PU array 1. In the figure, 16 is a microprocessor MPU, 17 is an arithmetic operation unit APU, 18 is a control register CR,
19 is status register SR, 20 is local memory
LM, 21 is program memory PM, 22 is result memory RM, 22a is synchronization register SC, 23 is front communication memory CM, 24 is rear communication memory
CM, 25 indicates the left communication memory CM, and 26 indicates the right communication memory CM.

The microprocessor MPU 16 executes application programs, performs 8-bit fixed-point arithmetic operations and logical operations, transfers data between memories, controls the arithmetic operation unit APU 17, and the like.

The arithmetic unit APU has 16-bit and 32-bit
It performs bit-width fixed-point arithmetic operations, 32-bit wide floating-point arithmetic operations, and basic function calculations such as logarithms and square roots. Transfer to the APU 17 and the start of its operation are completely controlled by the MPU 16. However, regarding these data,
Data can be transferred directly between the APU and memory without going through MPU registers.

Control register CR18 is connected to control register CR18 from control unit 2.
Used to transfer control words to the PU.

The status register SR19 is used to notify the control unit 2 of the status of the PU. This register is written by the PU and can only be read by the control unit 2.

Local memory LM20 is used to store local data and programs of the PU.

Program memory PM21 is used to store programs and read-only data.

The result memory RM22 is connected to the PU and control unit 2.
and is used to transfer data between them.

The synchronization register 22a is used to synchronize the processing of each PU in the PU array.

The communication memories CM23 to CM26 are connected to the front,
It is shared between the rear, left and right adjacent PUs, and used for data communication between each PU.

Each PU is synchronized by a system clock. The system clock is supplied by control unit 2. Access to the CM between adjacent PUs is controlled so that even-numbered PUs access it in half a system clock cycle and odd-numbered PUs access it in the other half cycle to avoid contention between PUs. .

(3) Data transfer between adjacent PUs Data transfer between adjacent PUs is performed using the above-mentioned front, rear, left and right communication memories CM23 to 26. Conventionally, local memory LM2
If you want to transfer the data in 0 to another adjacent PU,
MPU16 reads data in LM20 and stores it in communication memory CM23, 24, 25, 26
This was done by storing them sequentially.

However, this takes too much time for communication, so in the present invention, the MPU 16 is
When storing data in the CM 23 to CM 26, if the data is to be transferred to an adjacent PU, a special address (or address area) is designated and the data is written in the CMs 23 to 26 at the same time.

Figure 3 is seen from MPU16 of one PU.
An example of LM and CM address spaces is shown. Addresses 0 to 99 are areas that are accessed only to the LM20, addresses 100 to 199 are areas that are accessed only to the CM23 in front.
Areas that are commonly accessed with LM20,
Addresses 200 to 299 are areas commonly accessed by the rear CM24 and LM20, addresses
Addresses 300 to 399 and addresses 400 to 499 are areas commonly accessed by the left and right CM25, 26 and LM20, respectively, and address 500
599 is an area that is commonly accessed by the CMs 23 to 26 on the front, rear, left and right sides and the LM 20.

As a result, in each PU, the MPU 16 selects the LM2 according to the direction of the adjacent PU to which data should be transferred.
By selecting the write address area to 0, communication can be freely performed between adjacent PUs.

In this case, the arrangement of the PU array is not limited to two dimensions;
It can be applied to objects of any dimension, such as one dimension or three dimensions.

(4) Data transfer between the memories of multiple PUs or between the memory of a PU and a peripheral device Direct memory access (DMA) between the memories of multiple PUs in PU array 1 or between the memory and a peripheral device Data transfer is performed according to the method.

Conventional DMA controllers were created to transfer data between the memory of one PU and peripheral devices, so the following methods have been used to use them for multiple PUs: was.

Figure 4 is a schematic diagram of the system. In the figure, 1 is a PU array, 2 is a control unit, 27 is a PU connection switching circuit, 28 is a common bus, and 29 is a data transfer control device with a DMA controller function. . The control unit 2 uses its software to
PU connection switching circuit 27 provided for PU
PU or
Select and specify the PU group. As an example, a case where the contents of the memory of PU (01) are broadcast to the memories of all PUs from PU (00) to PU (73) is shown below.

First, the control unit 2 is connected to the PU connection switching circuit 2.
7 and connects the common bus 28 and PU (01).

Next, the data transfer control device 29 having a DMA controller function is informed of values such as the address of the memory to start reading and the amount of data, and the control right is transferred to this device 29.

Then, the data transfer control device 29 transfers PU (01)
The data is read from the memory of the control unit 2, temporarily stored in the memory of the control unit 2, and the control right is returned to the control unit 2.

The control unit 2 controls the PU connection switching circuit 27 to switch the common bus 28 from all PR (00) to PU
Connect with (73).

Next, the control unit 2 notifies the data transfer control device 29 of the address to which the data should be written, and transfers control.

The data transfer control device 29 releases the control right after writing the previously stored data into the memories of all PUs at the same time.

Through the above six steps, the contents of the memory of PU (01) are copied to the memories of all PUs.

However, this method provides relatively free PU selection and
Although it is possible to specify this, it has the disadvantage that it takes time to control and the efficiency of the entire system decreases.

In order to solve the drawbacks of the conventional method as described above, the present invention automatically reads and writes data in conjunction with the data read/write address indicator and data counter in the data transfer control device 29. An indicator is provided to select and control the desired PU or PU group, thereby reducing the time required for data transfer control and improving the processing efficiency of the PU array.

FIG. 5 is a configuration diagram of one embodiment of a data transfer control device based on the present invention. In the figure, 31 is a read PU indicator, 32 is a write PU indicator, 33 is a read address indicator, 34 is a write address indicator, 35 is a data latch, 36 is a read/write switch, 37 is a transfer data number indicator, 38 39 is a transfer data number counter, 39 is a comparator, 40 is an instruction register, 41 is an instruction interpreter, 42 to 45 are arithmetic units, and 46 to 48 are switches. less than,
Explain the functions of each part.

Read PU indicator 31, write PU indicator 32: PU from which data is read, and
A register that stores a code that specifies the PU to be written to. When that code is output to the PU selection bus, the address bus and data bus are connected to the specified PU, making it possible to read and write data from that PU. becomes. Arithmetic units 42 and 43 attached to the read PU indicator 31 and the write PU indicator 32 perform calculations to obtain the code of the next PU to be read and written after reading or writing from a certain PU is completed. It is something.

Read address indicator 33, write address indicator 34: These are registers that store an address from which data is read and an address where data is written, respectively. Arithmetic units 44 and 45 attached to the read address indicator 33 and the write address indicator 34 perform calculations to obtain the code of the next address to be read or written after reading or writing to a certain address is completed. It is something.

Data latch 35: Temporarily stores data to be transferred.

Read/write switcher 36: When this device transfers data, it performs control to alternately switch between reading and writing data. When reading data, flip switches 46, 47, and 48 upward, and set the read PU indicator to the PU selection bus.
Connect the read address indicator to the address bus, put the data latch 35 in the input state,
Set the READ/WRITE signal to READ state. In this state, data is read from the PU and temporarily stored in the data latch 35. Next, when writing data, turn down the switches 46, 47, and 48, connect the write PU indicator to the PU selection bus, and connect the write address indicator to the address bus.
Set data latch to output state, READ/WRITE
Set the signal to WRITE state. In this state, data is transferred from the data latch 35 to the PU.

Transfer data number indicator 37: A register that stores the number of data to be transferred.

Transfer data number counter 38: A register that counts and stores the number of transferred data.

Comparator 39: Compares the contents of the transfer data number indicator 37 and the contents of the transfer data number counter 38, that is, the number of data to be transferred and the number of transferred data, and transfers the necessary number of data. Detect what has happened.

Instruction register 40: This is a register that stores an instruction that instructs what procedure to perform data transfer. This command is decoded by the command interpreter 41 and instructs each of the calculation units 42 to 45 at appropriate timing what kind of calculation to perform.

For example, the memory of each PU No. 5, No. 10, and No. 15
The 8 data from address 100 are stored in the memory of all PUs.
If you want to move to address 300, read PU indicator 3
1, store a code representing all PUs in the write PU indicator 32, store 100 and 300 in the read address indicator 33 and write address indicator 34, respectively, and set 8 to the transfer data number indicator 37. Store it. Next, when an instruction instructing data transfer of this procedure is stored in the instruction register 40, this instruction is decoded by the instruction interpreter and execution begins.

First, the transfer data number counter 38 is cleared and 5
Data is read from address 100 of the numbered PU, and all
Written to address 300 of PU. After that, read address indicator 33, write address indicator 3
4. The value of the transfer data number counter 38 is incremented by 1.
The values of the read address indicator 33 and the write address indicator have been incremented by 1 and become 101 and 301, respectively, so next, start from address 101 of the 5th PU to all PUs.
Data is transferred to address 301. When this is repeated eight times, the values of the transfer data number indicator 37 and the transfer data number counter 38 become equal, a match is detected by the comparator 39, and the result is transmitted to the command interpreter 41. At this timing, the instruction interpreter 41 increments the read PU indicator 31 by +5, stores the original value 100 in the read address indicator 33, clears the transfer data number counter 38, and continues execution. number 15
When the data transfer from the PU is completed, the completion of all instructions is detected and the bus is released.

Furthermore, in complex computer systems, it is often necessary to copy several pieces of data scattered across each PU to all PUs. FIG. 6 shows another embodiment of the configuration of a data transfer control device that performs such copying.

In FIG. 6, only the elements different from those in FIG. 5 are shown: 49 is a read start address latch;
is the write start address latch, 51 is the transfer PU
52 is a transfer PU number counter, 53 is a comparator, and 54 to 56 are +1 adders. less than,
The operation of the device will be explained.

The number (code) of the PU to start reading is stored in the read PU indicator 31, the code representing all PUs is stored in the write PU indicator 32, and
The read start address latch 49 and the write start address latch 50 store the address to start reading and the address to start writing, respectively, the number of data to be transferred is stored in the number indicator 37, and the total number of PUs is stored in the number of transfer PUs indicator 51. Then, a copy instruction is stored in the instruction register 40.

Execution begins when the instruction is stored. The write start address is transferred to the write address indicator 34.

Clear the transfer data number counter 38, read the read start address, and read the address indicator 33.
Transfer to.

Read data from the address specified by the read address indicator 33 of the PU specified by the read PU indicator 31, and read data from the address specified by the write address indicator 34 in the PU specified by the write PU indicator 32. Write.

The values of the read address indicator 33, write address indicator 34, and transfer data number counter are +
Do 1. If the values of the transfer data number indicator 37 and the transfer data number counter 38 are not equal, the process returns to step.

When the values of the transfer data number indicator 37 and the transfer data number counter 38 become equal, the values of the read PU indicator 31 and the transfer PU number counter 52 are incremented by 1. Transfer PU number indicator 51 and transfer PU number counter 5
If the values of 2 are not equal, return to step 2.

Transfer PU number indicator 51 and transfer PU number counter 52
If the values are equal, the transfer ends, the bus is released, and control is returned to the parent computer or PU array.

Read PU indicator 31, write PU indicator 3
2, the computer within the control unit can also be specified. In this way, the structure of data can be rationally transferred between any PU and the memory of the control unit or the peripheral device according to the structure of the PU array.

(5) Connection between PU array and host computer In the present invention, a PU array 1 as shown in FIG.
For data reference between the computer 3 and the host computer 3, simple and fast bus coupling means are used. Regarding the PU array, apart from considering how the PUs are actually physically connected to each other, it is possible to consider the logical structure of the PU array as seen from the host computer.

Figure 7 shows 8 PUs, PU(0) to PU
(7) is an example of a PU array with a one-dimensional structure arranged in a row. On the other hand, data handled within a host computer can also have a logical structure. Figure 8 is 8x8
This is an example of two-dimensional matrix data. When this data is divided and processed using the PU array shown in Figure 7,
There are various ways of dividing. For example, PU (0) will share one column from a ₁₁ to _{a 81} , and a ₁₂ to _{a 82}
PU(1) shares one column of , and so on, each PU
It is conceivable that each column is divided into two columns.
In such a case, in the host computer,
The data is stored in the memory or peripheral device in the order numbered in parentheses in the matrix of FIG. On the other hand, in the PU array, 8 of (0) to (7)
are stored in each PU at addresses in that order.

As a more complex example, consider a PU array with a two-dimensional structure of 2 x 4, as shown in Figure 9.
In this case, the 8×8 matrix data can be divided into eight 4×2 small matrices and assigned to each PU. At this time, for example, the order (address) of data assigned to PU(0) and PU(1) is shifted as shown in FIG. 10A and B, respectively. Similarly, other
There is also a certain deviation in the data order in the PU from the data order in the host computer.

In the present invention, this misalignment is corrected between the address line and the PU
Using a conversion circuit that is automatically generated by simple calculations with the signal on the selection line, the corresponding data can be referenced between the host computer and the PU array at high speed.

Figure 11 shows the eighth
The 8×8 matrix data shown in the figure is converted to the 2× matrix data shown in FIG.
4 shows an example of an address conversion circuit for allocation to a PU array structure of 4. In the figure, 1 is a PU array, 3 is a host computer, 61 is an address line, 62 is a subtraction circuit that subtracts the address of _a11 in the host computer 3, that is, the start address, from the address line signal, 63 is a division circuit, and 64 is an addition circuit. Circuit, 65 is PU selection line, 6
6 is the PU address line. 62,63,6
The circuit No. 4 constitutes a conversion circuit and is placed within the control unit 2. The division circuit 63 divides the address signal into 1
The number of rows of data in one PU, i.e., the quotient b ₁ divided by "4" according to Figure 10, and the remainder b ₀ are calculated, and the quotient b ₁ is divided by the vertical number of PUs, i.e. "2", b ₃ and the remainder b ₂ , and then divide the quotient b ₃ into one
Find the number of columns of data in the PU, that is, the quotient b ₅ divided by "2" and the remainder b ₄ according to Figure 10, and calculate b ₀ , b ₂ ,
Output b ₄ and b ₅ .

Generally, the PU in the m row and n column in the PU array is
When expressed as (m, n), b ₅ , b ₂ gives PU(b ₅ ,
b ₂ ) is selected. However, as shown in Figure 11, if the PUs are numbered one-dimensionally from 0 to 7, the number will be b ₅ × (number of rows in the PU array) + b ₂ . .

b ₄ and b ₀ are the two-dimensional positions of the selected data in the PU selected by b ₅ and b ₂ as described above.
(b ₄ , b ₀ ), that is, b _4th row and b _0th column. If this is expressed as a one-dimensional address, it becomes b ₄ × (number of rows of data array in PU) + b ₀ + (base address in PU).

Here, as shown in FIG. 11, the address value of the address line 61 is A ₀ , the output address value of the subtraction circuit 62 is A ₁ , b ₄ and b ₀ , and the values of A ₂ , b ₅ and b ₂ are
Assuming that the value of is A ₃ , the value of the PU selection line 65 is A ₃ , and the value of the PU address line 66 is A ₄ , A ₁ , A ₂ ,
A ₃ and A ₄ are given by the following formulas.

A ₁ = A ₀ - (host computer start address) b ₀ :A ₁ / (number of rows of data array in one PU)
Remainder b ₁ :A ₁ / (number of rows of data array in one PU)
The quotient of b ₂ : b ₁ / (the number of vertical rows in the PU array) is the remainder b ₃ : the quotient of b ₁ / (the number of vertical rows in the PU array) b ₄ : b ₂ / (the data array in one PU) number of columns)
Remainder b ₅ :b ₃ / (number of columns of data array in one PU)
Quotient of A ₂ = b ₄ × (number of rows of data array in one PU) +
b ₀ A ₃ = b ₅ × (number of rows of data array in one PU) +
b ₂ A ₄ = A ₂ + PU base address In the case of the embodiment shown in Fig. 11, address line 61
The lowest two bits of _b0 specify one of the four data positions (order) in each column of the 4x2 matrix data assigned to each PU as shown in Figure 10 A and B. do.

The third bit from the bottom of address line 61 is
b ₂ , the PU in the first row of the 2×4 PU array
or the second line PU.

The fourth bit from the bottom of address line 61 is
As b ₄ , specify whether it is the first column or the second column of the 4×2 matrix data in each PU.

The 5th and 6th bits from the bottom of the address line 61 specify one of the four column positions in the PU array as _b5 .

In this example, the data row, column, PU row,
Since the number of columns is all a power of 2, the operation of the division circuit 63 can be completed by simply replacing the address lines. However, in the case of general numbers of rows and columns, the above division is necessary. b ₅ and b ₂ obtained by the calculation are used as selection line signals of the PU, and the base address of this data group in the PU is added to b ₄ and b ₀ in the adder circuit 64, and the output is Used as PU address line signal. With the above correspondence,
The host computer 3 can quickly refer to the data distributed in the PU array as the structure shown in FIG.

Since the above method provides a general address conversion method, it can also be applied to data structures other than the above example (such as three-dimensional data) and other PU array structures.

(6) Synchronization between PUs In order for each PU in the PU array to execute the next process, the results of the current process of the other PUs may be required. In such a case, all PUs in the PU array must be
must have finished its current processing. In the conventional synchronization control circuit, as shown in FIG. 12, each PU has a one-digit flag register 67, which is normally set to "0". "1" is written to each flag when the current operation is completed, and the match of these flags is detected by the AND gate 68.
The control device 69 determines that the output of the AND gate 68 is “1”
After that, I tried to synchronize by interrupting each PU.

However, if it is necessary to synchronize multiple locations in a program, synchronization must be achieved at each location, but the method shown in Figure 12 identifies each synchronization point for such multiple synchronization requests. Therefore, there is a possibility that synchronization control may be performed even for PUs at different synchronization points due to an error. In order to prevent such a problem from occurring, after the output of the flag register becomes "1", the control device needs to check whether the synchronization requests of each PU are of the same type. This is done by the controller examining each PU in turn, so
This will cause a decline in the performance of the entire system.

Therefore, in the synchronization control circuit of the present invention, a synchronization register having multiple digits is provided instead of a single-digit flag register, and different synchronization codes are set for different synchronization points to enable identification.

FIG. 13 is a schematic diagram thereof, in which 70 indicates a synchronization register and 71 indicates a coincidence detection circuit.

When the synchronization codes written in each synchronization register 70 match, the match detection circuit 71 notifies the control device 69 of the match and the synchronization code. The control device 69 achieves synchronization by instructing each PU to restart. As a result, even if there are multiple synchronization points, synchronization can be achieved reliably and quickly at each synchronization point.

Furthermore, by notifying the control device of the matched synchronization code, the control device can perform not only simple synchronization but also other controls such as stopping the PU.

FIG. 14 is a block diagram of one embodiment of a synchronous control circuit, and shows an example of synchronous control of a PU using a DMA request. In the figure, 2 is a control unit, 72 is a PU,
73 is an OR gate, 74 is a synchronization request flag register SF, 75 is a communication request flag register CF, 76
is a synchronization register SC, 77 is a coincidence detection circuit, 78
are OR and NOR gates, 79 is AND and OR
Gate, 80 is timer, 81 and 82 are AND
It is a gate. Next, the operational functions of the circuit will be explained.

In synchronization, the PU that has executed up to the synchronization point in the program temporarily stops execution by setting hardware that applies HALT, WAIT, etc. to itself, and detects that all PUs have entered this state. This is done by having the PUs all at once resume execution. However, when using a microprocessor that does not have a HALT state,
Use the method of stopping the PU using a DMA request. The PU that executed up to the synchronization point
By setting hardware that applies DMA instead of HALT or WAIT, execution is temporarily stopped, and when all PUs are detected to be in this state, execution is stopped at once by releasing DMA requests to the PUs all at once. This is done using the method of starting.

In order to make sure that the synchronization point does not shift for each PU, the PU writes a multi-bit synchronization code to the synchronization register SC, and releases the HALT request after detecting that the synchronization codes of all PUs match. .

Depending on the synchronization, even if a match is found, the
There is a case where the control unit 2 is notified without releasing HALT, so in that case, the communication request flag register CF is used to generate a notification request to the control unit.

When using DMA requests instead of HALT and WAIT, since DMA is generally used for data transfer, it is necessary to distinguish DMA requests for synchronization from those for data transfer. To do this, the DMA flag for data transfer and the DMA flag for synchronization (synchronization request flag register SF) are provided independently from each other, and the logical sum (OR gate 73) of the two is used to determine whether the actual PU
cause a DMA request to occur.

Detection of synchronization errors. Even though there is at least one synchronization request, if the contents of each synchronization register SC remain inconsistent for a certain period of time, the timer 80 detects this and notifies the control unit. This fixed time setting, ENABLE/
DISABLE is performed by software from the control unit.

The synchronization request flag register SF is a synchronization register.
Set by writing to SC and written to PU itself.
Generates a HALT (or WAIT, DMA) request.
Then, it is reset by releasing HALT for synchronization. A circuit that predetermines the default (usual value) of the synchronization register SC without providing special hardware for a flag such as a flip-flop, and interprets it as a synchronization request when it becomes a value other than that value. It can also be done by

The communication request flag CF to the control unit is set/reset by writing to the synchronization register SC, and generates a notification request to the control unit.

A synchronization code is written to the synchronization register SC only from the PU.

In this synchronous circuit, all SF is 1 and all SC
matches and CF is 0, for synchronization of all PUs
Cancel HALT request and flag. When CF is 1, interrupts the control unit.

Figure 15 shows an example of using signals such as HALT and WAIT that are separate from the DMA request when possible to achieve synchronization, and the synchronization code is set to the usual value instead of the synchronization request flag. This is a method that detects the absence and performs synchronous control. In the illustrated circuit, zero is used as the normal value of the synchronization code, so synchronization control is performed when the synchronization registers SC of all PUs take the same non-zero value. 83 in the figure is a coincidence detection circuit that detects that all inputs are the same non-zero value.

The operation of the circuit shown in FIG. 15 will be explained. First, the PU whose program execution has reached a synchronization point writes a non-zero synchronization code to the synchronization register SC. HALT is applied to PU in conjunction with writing to SC. each
PU writes synchronous code one after another and stops,
When the general detection circuit detects that all synchronization codes match and are not zero, its output signal clears all SCs. Furthermore, HALT of PU is canceled in conjunction with this, and all PU
will resume execution all at once.

Note that the circuits shown in FIGS. 14 and 15 can be used with different combinations of synchronous control conditions. That is, the synchronization request flag and
You can use HALT or something like that, or you can use the normal value of the synchronization code and DMA. It is also possible to add a communication request to these circuits or the circuit shown in FIG. Using the synchronization request flag and WAIT signal,
FIG. 16 shows an example of a circuit that generates a communication request when the value of the synchronization code is within a certain range.

In FIG. 16, 84 is a coincidence detection circuit that identifies coincidence of all inputs and whether it is positive or negative. Next, the first
The operation of the circuit shown in FIG. 6 will be explained. First, the PU whose program execution has reached the synchronization point registers the synchronization register SC.
Write the synchronous code in. At this time, negative synchronization codes are written at synchronization points where communication is necessary, and positive synchronization codes are written at synchronization points where communication is not necessary.
Synchronous request flag (SF) in conjunction with SC writing
is set, WAIT is applied to the PU, and the PU stops. Each PU writes synchronization code one after another,
When the synchronization detection circuit 84 detects that all synchronization codes match and are positive, all SFs are cleared by the output signal. In conjunction with this, PU WAIT is canceled and all
PUs resume execution all at once. When the synchronization code is negative, the coincidence detection circuit 84 transmits a communication request to the control unit of the parent computer.

〔Effect of the invention〕

As described above, according to the present invention, the communication time between each element computer or between a peripheral device and an element computer in a composite computer system is shortened, and synchronization control can be performed reliably, thereby improving the performance of the entire system. can be improved.

[Brief explanation of drawings]

Figure 1 is an overall configuration diagram of a composite computer system according to the present invention, and Figure 2 is a diagram of one of the components in the PU array.
A detailed configuration diagram of the PU, Figure 3 is an explanatory diagram of the address space of the communication memory CM, and Figure 4 is a schematic diagram to explain a conventional example of data transfer to the PU array.
FIG. 5 is a configuration diagram of one embodiment of a data transfer control device.
Figure 6 is a block diagram of another embodiment of the data transfer control device, Figure 7 is a diagram showing an example of a PU array with a one-dimensional structure, and Figure 8 is an explanatory diagram of 8x8 two-dimensional matrix data. , Fig. 9 is an explanatory diagram of a PU array with a two-dimensional structure of 2 × 4, Fig. 10 A and B are explanatory diagrams showing the data arrays in PU (0) and PU (1) in Fig. 9, respectively. Fig. 11 is a block diagram of one embodiment of an address conversion circuit, Fig. 12 is a diagram showing an example of a conventional synchronous control circuit, Fig. 13 is a schematic diagram of a synchronous control circuit according to the present invention, and Fig. 14 is a synchronous control circuit. A block diagram of one embodiment of the circuit, and FIGS. 15 and 16 are block diagrams of other embodiments of the synchronous control circuit, respectively. In the figure, 1 is the PU array, 2 is the control unit, and 3 is the PU array.
is a host computer, 16 is a microprocessor MPU, 20 is a local memory LM, 22a is a synchronization register SC, and 23 to 26 are communication memories CM.
shows.

Claims (1)

[Claims] 1 In a composite computer system in which multiple computers are arranged in parallel and communication is possible between two adjacent computers, each computer has a local memory, and each adjacent two
A communication memory is provided between two computers, and a common address area is set in at least a part of the local memory and communication memory for each computer, and each computer uses the common address area when communicating with an adjacent computer. A composite computer system characterized in that the same data is simultaneously written to both local memory and communication memory using .