JPH027135A - Watch dog timer circuit - Google Patents

Abstract

PURPOSE:To secure strict monitoring capacity for a watch dot pulse abnormality by setting a periodical monitoring period T1 for a peak watch dog pulse longer than a monitoring period T2 for the watch dog pulse except it. CONSTITUTION:After a CPU 10 is reset, a peak watch dog pulse 12 generated by the CPU 10 through a time-up time variable setting circuit 13, set a time-up time T of a watch dog timer circuit II to T1. For this reason, even when the circuit 11 passes through from t0, the circuit does not generate the resetting signal, a peak watch dog pulse is inputted by t1, and then, it is reset by this and a counting action for the next watch dog pulse is started. This depends on the fact that a deciding circuit 12 makes the time-up time variable setting circuit 13 reset the time-up time T of the watch dog timer circuit 11 to the T2 shorter than the T1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer (hereinafter also referred to as a microcomputer), and particularly to a watchdog timer circuit for a microcomputer.

[Conventional technology]

Conventionally, in micro and computers, so-called watchdog timers have been used to detect runaways, abnormalities, etc. in software or hardware. This means that if the microcomputer is operating normally, a pulse (watchdog pulse) indicating this is sent at a predetermined maximum cycle T. The output is repeated at the following intervals, and the timer
(Tsuchido knob timer) repeatedly to reset the
If the output lag pulse is missing or the period exceeds the predetermined set time-up time (monitoring period) T, the
When the Nochidog timer times up, a reset signal is output to the microcontroller, causing the microcontroller to perform a predetermined operation (exception processing) such as resetting/restarting or outputting an alarm using a reset/reset interrupt. be.

[Problem to be solved by the invention]

A microcomputer having the above-mentioned watchdog timer has the above-mentioned maximum period T immediately after each reset operation such as a power-on reset. The war dog pulse must be output within the following range. It is T after the microcontroller is reset with the power supply voltage rising. If the watchdog timer's set time-up time (monitoring period) T is reached without the first watchdog pulse being output even after the watchdog timer is reset.
The microcomputer is reset again by outputting the reset signal, and the watchdog pulse after this reset is also T. This is because the reset signal is output from the watchdog timer to the microcomputer and the reset operation is repeated, making it impossible for the microcomputer to enter a stable operating state.

However, immediately after a microcomputer is reset, it generally initializes the entire system including the microcomputer, performs initial self-diagnosis, etc., and then starts periodic control and outputs a watchdog pulse to confirm its operation. In particular, since the time required for such initial processing is often longer than the control cycle for subsequent stable operation, the maximum cycle T described above starts immediately after reset. It is not easy to output a watchdog pulse within the range of 200 to 3000, and the program must become more complex to make this possible.

Also, in relation to this point, there tends to be a large difference in the period of the watchdog pulse between the initial processing and the subsequent periodic control, and the watchdog timer does not operate (reset signal output) within this error range. In order to do this, it was necessary to increase the tolerance of the time-up time T of the watchdog timer, and the ability to monitor abnormalities in the watchdog pulse or the sensitivity to detect abnormalities had to be reduced accordingly. .

The present invention was made in view of the above circumstances, and its purpose is to provide a watchdog timer circuit for a microcomputer that can ensure high abnormality detection sensitivity without complicating the program.

[Means to solve the problem]

To achieve the above object, the present invention provides a predetermined maximum period T from a normally operating microcomputer. It is reset by a watchdog pulse that is input at the following cycles, and when the next watchdog pulse is not input even after a set time-up time (monitoring period) T that is longer than the maximum cycle T0 after the reset, In a watchdog timer circuit that outputs a reset signal to a microcomputer as a watchdog pulse period abnormality, the above time-up time T is set to T for the first watchdog pulse (first watchdog pulse) output after the microcomputer is reset. =T, and subsequent watchdog pulses are set to T=T2, and are variably set to the relationship TI>T2.

[Effect]

In the watchdog timer circuit of the present invention having the above configuration, for the first watchdog pulse output after the microcomputer is reset, the time-up time (monitoring period) T of the watchdog timer circuit is the same as that of the subsequent microcomputer. T is longer than the time-up time T2 for the watchdog pulse (maximum period T) during stable operation.

Since it is set to , the first wo, 2nd, gu, and <rus are this T. Even if the watchdog timer circuit is output much later than T2, the watchdog timer circuit will not output a reset signal (the microcontroller can smoothly transition to normal control operation. Therefore, the first watchdog timer circuit will not output a reset signal. Immediately after, there is no need to prepare a special program to output within the above-mentioned maximum period T, and it is possible to avoid complicating the program.

Also, the maximum period T other than the first watchdog pulse. The time-up time T2 of the watchdog timer circuit for the watchdog pulse is T.

Since the time-up time can be brought sufficiently close to , it is not necessary to take a large tolerance for time-up time as in the conventional case, and the abnormality monitoring ability or abnormality detection sensitivity of the microcomputer operation can be improved.

〔Example〕

Embodiments of the watchdog timer circuit of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the main parts of a microcomputer system to which an embodiment of the watchdog timer circuit of the present invention is applied.
The watchdog timer circuit If includes a leading watchdog pulse discrimination circuit 12 and a time-up time variable setting circuit 1.
It is equipped with 3. Microcomputer (CPU) 1
The output of the differentiating circuit 14 that differentiates the G watchdog pulse W is input to the watchdog timer circuit 11 and the first watchdog pulse discriminating circuit 12, and the power supply voltage monitoring circuit I5 monitors the power supply voltage and detects when the voltage falls below a predetermined value. A signal is output to the watchdog timer circuit II.

The watchdog timer circuit II monitors the watchdog pulse W input through the differentiator circuit t4, and when the period thereof is not within the set time-up time (monitoring period) T, a reset signal is sent to the terminal of the CPU 1. Output to.

The watchdog timer circuit 11 is a power supply voltage monitoring circuit 1.
Similarly, when the output signal No. 5 is input, a reset signal is output. Watchdog timer circuit! The reset signal 1 is also input to the leading watchdog pulse discrimination circuit 12.

The time-up time T of the watchdog timer circuit 11 is the maximum cycle T of the watchdog pulse during normal stable control operation of the microcomputer IO. The time-up time variable setting circuit 13 makes T=T longer by a predetermined allowable time.
, or variably set to T=T2 (T,>T2>To). The leading watchdog pulse determination circuit 12 determines whether the watchdog pulse W inputted via the differentiating circuit 14 is the first watchdog pulse (leading watchdog pulse) after the microcomputer 10 is reset, and determines whether the leading watchdog pulse is the leading watchdog pulse. If there is, use the time-up time setting circuit 13 as a watchdog timer circuit! Set the time-up time of ■ to T=T, and at other times T=
Set it to T2.

Now, 1=1 in Figure 2. Assuming that the reset operation of CPU10 is completed, the watchdog pulse generated by CPtJlo immediately after that is the first watchdog pulse, so the first watchdog pulse 12 is sent to the time-up time variable setting circuit 13 and the watchdog timer circuit 11.
The time of the time is T.

Set it to Therefore, even after T2 has elapsed from to, the watchdog timer circuit 11 does not issue a reset signal.
1. When the first watchdog pulse is input, the timer is reset (the timer contents become zero) and starts counting the time for the next watchdog pulse. Of course, if the first watchdog pulse is not input even after T1, the watchdog timer circuit 11
Outputs a reset signal to Ul0.

As mentioned above, 1. If the first watchdog pulse is input before T, the first watchdog pulse determination circuit 12 sets the time-up time T of the watchdog timer circuit 11 to T2, which is shorter than T1, in the time-up time variable setting circuit I3. Let me fix it. However, this T2 is the period of watchdog pulses other than the first watchdog pulse, which have long periods, that is, the maximum period T. longer (TI > T2 > To).

Thereafter, the watchdog timer circuit U continues to monitor the cycle while being repeatedly reset by the watchdog pulse W (after t2) from the CPUIG, with T2 as a time-up time, ie, a monitoring period.

Then, for example at t3, the timer content is T2
If the watchdog pulse is not input until
Watchdog timer circuit 11 outputs reset signal 1
．． , CPU10 is reset. After this reset, the watchdog timer circuit 11 restarts the time measurement operation from t4, but in this case as well, as in the case of 18 above, the leading watchdog pulse discriminating circuit 12 detects the time-up of the watchdog timer circuit 11 in the time-up time variable setting circuit. The time T is set to T1, and after being reset by the first watchdog pulse at t, that is, for subsequent watchdog pulses indicated at t6, T is set to T2.

FIG. 3 shows an example of a specific circuit configuration of the main part of the embodiment shown in FIG. Watchdog timer circuit 1 in Figure 3
1 is a first comparator Ill, a second comparator 112, and three S-
R latch S LL, 5RL2.5RL3.2 OR circuit 01! 1, an integral timer circuit 113, an output circuit 114, and the like. The integral timer circuit 113 includes a timer capacitor TC and a transistor Trl for switching charging and discharging of this capacitor, and the output circuit 114 includes a transistor Tr2 that supplies a 1EsET signal to the CPUI◎ when conductive.

The leading watchdog pulse discrimination circuit 12 includes an S-R latch 5IL4, and a time-up time variable setting circuit 13.
becomes conductive or non-conductive depending on the state of 5tL4, and the first comparator 111, ! 2 comparator 112 reference voltage V rafts Vr* (□). The differentiating circuit 14 consists of a normal RC differentiator 141, a diode clipper I42, output stage transistors Tr5, Tr5, etc., and a watch from CPU10. The dog pulse W is differentiated and a pulse synchronized with its leading edge is supplied to the S input terminal of the S-R latch 5ljL3.The power supply voltage monitoring circuit 15 is connected to a constant voltage power supply ( The output voltage v11. of the stabilized power supply) is set as the reference voltage V r of the Zener diode 201.
It consists of a comparator 151 whose output becomes high when V rag <Vrsf3 compared with @t3.

Hereinafter, the circuit operation of the embodiment shown in FIG. 3 will be explained in detail with reference to FIG. 4, which shows the operation timing of its main parts.

τ after power on. The stabilized power supply voltage V r @ g
rises above the reference voltage V r @ f 3, the output (■) of the comparator 151 of the power supply voltage monitoring circuit 15
becomes low, and the integral timer circuit 113 of the watchdog timer circuit 11 lowers the base voltage of the transistor Tri (■
) goes low and the timer capacitor TC starts charging.

Before τ0, the charging voltage Vtc (■) of the timer capacitor TC is the first comparator 111. Lower than the reference voltage V roll v, , □ of the second comparator 112, the output (■) of the first comparator 111 is /%-i,
Since the output (■) of the second comparator 112 is low, the output (■) of the S-R latch SH,1 is low. At this time, the output (■) of the comparator 151 is high, so the output (■) of the SR latch 5RL2 is high. Therefore, the transistor Tr2 of the output circuit 114 is conductive, and the RESET signal output (■) to the CPU 1O is low. Further, the transistor Trl of the integral timer circuit 113 is also conductive, and the timer capacitor TC is hardly charged.

On the other hand, S-R of the leading watchdog pulse discrimination circuit 12
Since the R terminal of latch 5IL4 is also high (■) and the S terminal is low (■), the output of S-R latch 5tL4 (
@) is low, the transistor Tr4 of the time-up time variable setting circuit I3 is conductive, and the first comparator 1
11. Since the resistor No. 1 of the reference voltage setting circuit of the second comparator 112 is shunted by the resistor R4, the resistor [
The currents of 2 and 13 increase, and the reference voltage v r-t 1 of the first comparator 11-the reference voltage V r @ f 2 of the second comparator 112 are both high (H) (■).

τ above. The voltage (■) of the timer capacitor TC that started charging at is the reference voltage Vret of the first comparator 111.
When xH is reached (τ,), the output (■) of the first comparator 111 becomes low. However, S-R latch 5ttl
The output (■) remains unchanged. When the charging of the timer capacitor TC progresses and the voltage (■) reaches the reference voltage V,...211 of the second comparator 112 (T2), the output (■) of the second comparator 112 becomes low, and the S-R latch 5R
Since the output of LI (■) and the base (■) of the transistor Trl of the integral timer circuit 3 become high, the timer capacitor TC is almost instantaneously discharged via the transistor Trl, while the distance report output (■) Low, S-R latch 5
The output (■) of the S-R latch sgt2 becomes low while the R terminal (■) of RL4 is kept high.

By discharging the timer capacitor TC, vTC instantly becomes v
Since it is lower than ref2■, the second comparator 112
The output (■) also becomes low instantaneously, and vTc becomes Vr*t1.
When the voltage is discharged to below H (T3), the output (■) of the first comparator Ill becomes NO1, and the output (■) of the S-R latch 5RLI and the base (■) of the transistor Trl of the integral timer circuit 113 become (2) becomes low (however, the state of the S-R latch 5liL2 remains unchanged), the transistor Tr2 of the output circuit 114 is turned off, and the RE
While the SET output becomes 7% (reset complete), the transistor Trl of the integral timer circuit 113 is cut off and the timer capacitor TC starts charging again. At this point, the R terminal (■) of the SR latch 5RL4 also becomes low, but the state of the SR latch 5RL4 does not change. Furthermore, since vTc immediately becomes equal to or higher than Vr*fl■ by the start of charging of the timer capacitor TC, the output (■) of the first comparator 111 also returns to low immediately, but the state of the S-R latch 5RL1 remains unchanged (■). output is held low).

vTc increases by charging the timer capacitor TC,
Since the watchdog pulse W is input, vr, 1
When □■ is reached (T4), almost the same operation as at T2 is repeated. However, in this case, S-R latch 5R
The output of L2 (■) does not change (maintains low), and the output of S-R latch S[,1 goes high until the time T5 starts charging the timer capacitor TC, which keeps it low. ■The n output (■) is supplied to the CPUIO, and the R terminal (■) of the S-R latch S1jL4 becomes high (however, the state does not change). Thereafter, the operations from T3 to T5 are repeated unless the watchdog pulse W is input or the output (■) of the power supply voltage monitoring circuit 15 becomes high due to a drop in the stabilized power supply voltage. In this case, from t 3 (Vtc=V rat +H) to T4
The time T until (vTc=V r e f□■) corresponds to the monitoring period for the first watchdog pulse immediately after reset (T=T,), and since the first watchdog pulse is not input within T1 here, Low RESE to CPU10 as watchdog pulse cycle abnormality
A T signal is output (T4).

After charging of the timer capacitor TC is restarted at T5 above, vTo reaches Vt, II gc: CPU1G
When the first watchdog pulse W is input to the differentiating circuit 14 (T6), the output (■) of the differentiating circuit 14, that is, S
-The S terminal of R latch 5RL3 becomes high, and its output (
[phase]) becomes high (at this time, reset completion (I
jESET signal low) causes R, terminal (■) low, V?
c> V r, t tH causes the R2 terminal (■) low condition), the transistor T of the integral timer circuit 113 becomes conductive, and the timer capacitor TC is almost instantly discharged (
(Resetting the integral timer circuit 113).

Also, at the same time that the S terminal of the S-R latch Si3 becomes negative, the S-R of the leading watchdog pulse discriminating circuit 12 becomes
Since the S terminal of latch S Ii:L4 also becomes negative and its output (@) becomes high, the transistor Tr4 of the time-up time variable setting circuit 13 is cut off, and the first
The reference voltage V rafl of the comparator 111 and the reference voltage V r * f 2 of the second comparator 112 decrease to V r @ 11 L and vref2L, respectively. At this time, even if the S terminal becomes low due to disappearance of the differential waveform of the watchdog pulse, the state of the S-R latch SRL4 does not change.

Note that the time-up time variable setting circuit 13 is provided with a delay circuit consisting of a capacitor C131, for example.
The transistor Tr4 is cut off after a slight delay after the input of the first watchdog pulse W. As a result, the first watchdog pulse W at T6
At the moment when is input, the reference voltage of the second comparator 112 becomes Vref2L, and Vtc>V r, tzL NiyosuS -R5ffsIjLl (Useless image signal output due to D output (■) becoming high is prevented. be done.

Due to the discharge of the timer capacitor TC, vTc becomes V r *
(When the voltage drops below IL, the output (■) of the first comparator 111 becomes high, and the S-R latch 5kL
Since the R2 terminal of 3 becomes high and its output ([phase]) becomes low, the transistor Tr4 becomes cut off,
Timer capacitor TC resumes charging. Due to this charging, Vtc>V, t+L, and the R terminal (■) immediately becomes low, but the state of the S-R latch 5RL3 remains unchanged. Hereafter, τ7. As in τ8, as long as the next watchdog pulse W is input before the charging voltage vTc of the timer capacitor TC reaches V r e f L after discharging due to the input of the previous watchdog pulse W, the integral timer The circuit 113 is connected to the CPU from the output circuit 114.
To l0, the clock operation for monitoring the watchdog pulse cycle is continued while repeating the same reset as in τ6 above without outputting the signal.

That is, after τ6, the cut-off of the transistor Tr4 of the time-up time variable setting circuit 13 causes the watchdog pulse cycle monitoring period T of the watchdog timer circuit 11 to become equal to the charging voltage V? of the timer capacitor TC. C is V,,
,, switches to T2 from L to Vr@f2L. Here, due to the series connection of resistors [2 and [3], V r-t
2■V r-tzL > V r,t +HV r-t
Since tL, T>72.

For example, if the watchdog pulse W is not input within T2 after resetting the integral timer circuit 113 at τ9 and the charging voltage VtC of the timer capacitor TC reaches V-f2L (τ10), the second The output (■) of the comparator 112 becomes high, the output (■) of the S-R latch 5RLI becomes high, the transistor R2 of the output circuit 1!4 becomes conductive, and the CPU10 low ■ signal is output. . Also, at the same time as the timer capacitor TC is discharged instantaneously, the R terminal (■) of the S-R latch 5RL4 becomes high, so its output (@) becomes low, the transistor Tr4 conducts, and the first comparator ii
i, the reference voltage of the second comparator 112 is again V, , , II.

Vrmt2'' becomes o 1:HteV1c is V, , lIH
As the T4-c drops, the S - η signal goes high (reset is completed) and charging of the timer capacitor TC is restarted, but the monitoring period T of the watchdog timer circuit 11 at this time is immediately after the reset. Because there is, it becomes T.

Then, when the first watchdog pulse (first watchdog pulse) W after reset is inputted from the CPU 10 at τ1□, the monitoring period is switched to T2 again, and all (the same operations as after τ6) are repeated. In the course of such an operation, for example τ,.

As in, the stabilized power supply voltage V11. is V r e
When f falls below 3, the output (■) of the comparator tSt of the power supply voltage monitoring circuit 15 becomes high and becomes τ. Returning to the previous state, the RESET signal output goes low. If the stabilized power supply voltage V r * * returns to normal (τ14
), the aforementioned τ. The subsequent operations are repeated.

〔Effect of the invention〕

As described above in detail, the watchdog timer circuit of the present invention has a cycle monitoring period T for the first watchdog pulse output after the microcomputer is reset, and a monitoring period T2 for other watchdog pulses. This allows the watchdog pulse to be set for a longer period of time without complicating the microcomputer program (and without sacrificing abnormality detection sensitivity), ensuring strict monitoring ability for watchdog pulse abnormalities. Therefore, it can contribute to improving the performance and reliability of microcomputers using watchdog timer circuits.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing the basic configuration of an embodiment of the watchdog timer circuit of the present invention, Fig. 2 is a timing diagram for explaining its operation, and Fig. 3 is a block diagram showing the basic configuration of an embodiment of the watchdog timer circuit of the present invention. FIG. 4 is a block diagram showing an example of a specific circuit configuration of the main part of the embodiment shown in FIG. 1, and FIG. 4 is a timing diagram for explaining its operation. 0...Microcomputer, ■...Watchdog timer circuit, 2...Top watchdog pulse discrimination circuit, 3...Time-up time variable setting circuit, 4...Differentiating circuit, 5 ...Power supply voltage monitoring circuit, 111...First comparator, 112...Second comparator, 113... Integral timer circuit, l14... Output circuit,
TC... Timer capacitor. same

Claims (2)

[Claims] (1) It is reset by a watchdog pulse inputted from a normally operating microcomputer at a cycle less than or equal to a predetermined maximum cycle T_0, and after reset, a set time-up time (monitoring period) T longer than the maximum cycle T_0 is set. If the next watchdog pulse is not input even after the elapse of time, the watchdog timer circuit outputs a reset signal to the microcomputer as a watchdog pulse cycle error. A watchdog characterized in that the outputted watchdog pulse (first watchdog pulse) is set as T=T_1, and the subsequent watchdog pulses are set as T=T_2, so that the relationship of T_1>T_2 is established. timer circuit. (2) A leading watchdog pulse discrimination circuit that discriminates between the leading watchdog pulse and other watchdog pulses, and a time-up time T of the watchdog timer circuit in response to the output of this leading watchdog pulse discrimination circuit. 2. The watchdog timer circuit according to claim 1, further comprising a variable time-up time setting circuit for variably setting T=T_1 or T=T_2.