JPH0271345A - Ic card - Google Patents

Ic card

Info

Publication number
JPH0271345A
JPH0271345A JP63223948A JP22394888A JPH0271345A JP H0271345 A JPH0271345 A JP H0271345A JP 63223948 A JP63223948 A JP 63223948A JP 22394888 A JP22394888 A JP 22394888A JP H0271345 A JPH0271345 A JP H0271345A
Authority
JP
Japan
Prior art keywords
lsi
switching circuit
main body
sensor
body case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63223948A
Other languages
Japanese (ja)
Inventor
Yoshinori Okita
大喜多 義憲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP63223948A priority Critical patent/JPH0271345A/en
Publication of JPH0271345A publication Critical patent/JPH0271345A/en
Pending legal-status Critical Current

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  • Storage Device Security (AREA)

Abstract

PURPOSE:To inhibit the alteration of an LSI by detecting a fact that the main body case of the LSI is opened via a sensor to turn on a switching circuit with the detection output of the sensor and applying a destructive battery to the LSI. CONSTITUTION:When a main body case of an LSI 4 is opened for alteration of the memory contents of the LSI 4, a solar battery 8 is irradiated by the light and generates the electromotive force. Thus both transistors Tr1 and Tr2 of a switching circuit 10 are turned on, and the collector voltage of both transistors have low levels. Then the gate voltage levels of the MOS transistors 6a and 6b are inverted by an inverter 12 into high levels. Thus both MOS transistors are turned off. While the gate voltage of the MOS transistors 14a and 14b of the circuit 10 are set at low levels. Thus both 14a and 14b are turned on. As a result, the LSI is destroyed.

Description

【発明の詳細な説明】 く技術分野〉 本発明は、ICカードに係り、特にはLSIのメモリ内
容の改ざんに対するセキュリティ技術に関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an IC card, and more particularly to a security technique against tampering with the memory contents of an LSI.

〈従来技術〉 ICカードにおいては、現行では本体ケースを開けてL
SI内部のメモリ内容を解析して改さんすることが可能
であり、セキュリティの面で問題がある。化なイ′)ち
、ICカードを、キャッシュカード、プリペイドカー1
・なとに使用4゛る場合、決済金額等が不正に改ざんさ
イすると金融取引の混乱や社会的な弊害をもたらす。し
たか−、て、LSIの改ざんに対して何等かの保護対策
か必要となる4、〈発明の[1的〉 本発明は、このような事情に鑑ゐてなされ八Gのであっ
て、LSIのメモリ内容の改さん行l)を確実に防止で
きるようにすることを1−1的とする。
<Prior art> Currently, with IC cards, the main body case is opened and the
It is possible to analyze and tamper with the memory contents inside the SI, which poses a security problem. *) Chi, IC card, cash card, prepaid car 1
・If the payment amount is fraudulently tampered with, it will cause confusion in financial transactions and cause social harm. However, some kind of protection measure against tampering with LSI is required. 4. <Object 1 of the Invention> The present invention has been made in view of the above circumstances, and is a Objective 1-1 is to reliably prevent the alteration of the memory contents of the line l).

〈発明の構成〉 本発明は、」−記の目的を達成するために、次の構成を
採る。
<Configuration of the Invention> The present invention adopts the following configuration in order to achieve the object stated in ``-''.

すなわち、本発明のICカートて(J、本体ケースの開
放を検出するセンサーと、こり)センサーの検出出力に
応答してオン動作するスイッチング回路と、LSIに対
して前記スイッチング回路を介して逆極性に接続された
LSI破壊用電池とを備えることを特徴としている。
That is, the IC cart of the present invention (J, a sensor that detects opening of the main body case, and a switching circuit that turns on in response to the detection output of the stiffness sensor), and a switching circuit that operates to turn on in response to the detection output of the sensor that detects the opening of the main body case, and a reverse polarity It is characterized by comprising an LSI destruction battery connected to the

上記構成によれば、LSIのメモリ内容を改ざんしよう
として本体ケースを開(すると、これがセンサーによっ
て検出される。このセンサーの検出出力によりスイッチ
ング回路かオン動作し、これに伴−)てり、SI破壊用
電池から[−S Iに対して逆バイアスが印加される。
According to the above configuration, an attempt is made to tamper with the memory contents of the LSI by opening the main body case (this is detected by the sensor. The detection output of this sensor turns on the switching circuit, and accordingly, the SI A reverse bias is applied to [-SI from the destruction battery.

そのノコめ、l−、S Iが破壊されるので、改ざスが
不可能となる、。
Since the saw, l-, SI is destroyed, tampering becomes impossible.

〈実施例〉 図は、LSI内部の電源回路部分の回路構成図である5
、同図において、1はIcカードの電源回路で、本体ケ
ースに内蔵されている。2はメイン電池、1はこのメイ
ン電池2から電源供給を受1[るLSI、6a、61J
はメイン電池2とL S I 4との間に介設されたI
)ヂャンネル型のMOS)ランノスタ、8は本体ケース
の開放を検出するセンサーとしての太陽電池、10は太
陽電池8の起電力によりオン動作するスイッチング回路
である。
<Example> The figure is a circuit configuration diagram of the power supply circuit part inside the LSI.
, In the figure, 1 is a power supply circuit for the IC card, which is built in the main body case. 2 is a main battery, 1 is an LSI that receives power supply from this main battery 2, 6a, 61J
is an I interposed between the main battery 2 and the LSI 4.
8 is a solar cell as a sensor for detecting opening of the main body case, and 10 is a switching circuit turned on by the electromotive force of the solar cell 8.

このスイッチング回路IOは、2つのトランジスタTr
+、 Tr、、谷トランジスタTr+、Tr2のベース
抵抗1工1、rz、とコレクタ抵抗R1、R4、インバ
タ12および一対のPヂャノネル型のM OS I・ラ
ンノスク14a、11bかt:、rjる。+6は、L記
のL S I 4に対し一ζスイッヂング回路10を介
して逆極性に接続されたLSI破壊用11^池である5
、次に、上記構成の動作について説明4゛る5、電源回
路Iは、本体ケースに内蔵、S打ているため、通常、太
陽電池の出力型l■:は(l vである5、このため、
スイッチング回路10の両トランジスタTrい11r、
はオフ状態(こあり、1.ノコか−)−ご、メイン電池
2による電圧はインバータ12てレベル反転されてMO
Sトランジスタ6a、6bのゲート電圧は〔1−レベル
とな−・ている。ニイ1により、MOS)−ランジスタ
ロa、6bfjオン状態と/a:’l、L S I 4
 i]J:メイン電池2から電jj;i市II、’ V
 ccか印加さイ]る。しから、この場合、スイッチン
グ回路10のMOS)ランノスタ14a、I4bのノr
ト電圧はハイレベルに紹持されているため、両MOS+
−ランジスタ14a、+ 41+ fJオ:ノ状態にあ
る。
This switching circuit IO includes two transistors Tr.
+, Tr, the base resistors 1, rz, and collector resistors R1, R4 of the valley transistors Tr+, Tr2, the inverter 12, and a pair of P-channel type MOSFETs 14a, 11b and t:, rj. +6 is an LSI destruction 11^ pond connected to the LSI 4 in L through the ζ switching circuit 10 with opposite polarity 5
,Next, we will explain the operation of the above configuration.4,5,Since the power supply circuit I is built in the main body case,,usually, the output type of the solar cell is,l,:,(l,v,5,. For,
Both transistors Tr11r of the switching circuit 10,
is in the off state (this is 1.nokoka-) - the voltage from the main battery 2 is level inverted by the inverter 12 and the MO
The gate voltages of the S transistors 6a and 6b are at the 1- level. By Nii 1, MOS)-Langistaro a, 6bfj on state and /a:'l, L S I 4
i] J: Power from main battery 2 jj; i city II, 'V
Apply cc. Therefore, in this case, the MOS of the switching circuit 10)
Since the voltage is introduced at a high level, both MOS+
-Ransistor 14a, +41+fJO: is in state.

この状態から、L S I 4のメモリ内容を改さんし
ようとして本体ケースを開(3ると、太陽電池8に光が
照射されて起電力か発!11゛ろ、、8の八め、スイッ
チング回路IOの両トランノフ、りi”r、、′I゛r
、が共にオンし、そのコレクタ電圧がそれぞれローレベ
ルになる。すると、MOSトランジスタ6a、6bのゲ
ート電圧はインバータI2でレベル反転されてハイレベ
ルとなるので、MOSトランジスタ6a、6bはオフ状
態となる。一方、スイッチング回路IOのMOSトラン
ジスタ14aS 14bのゲート電圧は〔1−レベルに
なるため、両MOSトランジスタ14a、14bがオン
状態になる。その結果、LSI破壊用電池16から1.
、 S 14に対して逆バイアスが印加されてLSIか
破壊されるので、改ざんが不可能となる。
From this state, in an attempt to modify the memory contents of the LSI 4, the main body case is opened (3), and the solar cell 8 is irradiated with light, generating an electromotive force! Both tranovs of circuit IO, rii”r, ′I゛r
, are both turned on, and their respective collector voltages become low level. Then, the gate voltages of the MOS transistors 6a and 6b are inverted in level by the inverter I2 and become high level, so that the MOS transistors 6a and 6b are turned off. On the other hand, since the gate voltage of the MOS transistors 14aS and 14b of the switching circuit IO becomes the [1- level], both the MOS transistors 14a and 14b are turned on. As a result, from 16 batteries for LSI destruction, 1.
, S14 is applied and the LSI is destroyed, making tampering impossible.

〈発明の効果〉 本発明によれば、本体ケースを開けるとLSIの破壊が
生じるため、L S Iのメモリ内容の改ざんが確実に
防止できるようになる。
<Effects of the Invention> According to the present invention, since the LSI is destroyed when the main body case is opened, tampering with the memory contents of the LSI can be reliably prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の実施例を示t I Cカードの電源回路
部分の回路構成図である。 I・1!椋回路、4・ LSI、8・センサー(太陽電
池)、10 ・スイッチング回路、+6−LS■破壊用
電池。
The drawing shows an embodiment of the present invention and is a circuit configuration diagram of a power supply circuit portion of a tIC card. I・1! Muku circuit, 4・LSI, 8・Sensor (solar cell), 10・Switching circuit, +6-LS ■Battery for destruction.

Claims (1)

【特許請求の範囲】[Claims] (1)本体ケースの開放を検出するセンサーと、このセ
ンサーの検出出力に応答してオン動作するスイッチング
回路と、 LSIに対して前記スイッチング回路を介して逆極性に
接続されたLSI破壊用電池と、 を備えることを特徴とするICカード。
(1) A sensor that detects opening of the main body case, a switching circuit that turns on in response to the detection output of this sensor, and an LSI destruction battery that is connected to the LSI with opposite polarity via the switching circuit. An IC card characterized by comprising the following.
JP63223948A 1988-09-07 1988-09-07 Ic card Pending JPH0271345A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63223948A JPH0271345A (en) 1988-09-07 1988-09-07 Ic card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63223948A JPH0271345A (en) 1988-09-07 1988-09-07 Ic card

Publications (1)

Publication Number Publication Date
JPH0271345A true JPH0271345A (en) 1990-03-09

Family

ID=16806208

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63223948A Pending JPH0271345A (en) 1988-09-07 1988-09-07 Ic card

Country Status (1)

Country Link
JP (1) JPH0271345A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08115267A (en) * 1994-10-19 1996-05-07 Tech Res & Dev Inst Of Japan Def Agency Information secrecy mechanism
WO1998053402A1 (en) * 1997-05-19 1998-11-26 Rohm Co., Ltd. Ic card and ic chip module
JP2000134196A (en) * 1990-11-16 2000-05-12 General Instr Corp Terminal update system to keep maintain communications network
US6433927B1 (en) * 1999-12-02 2002-08-13 Jds Uniphase Inc. Low cost amplifier using bulk optics
JP2006343844A (en) * 2005-06-07 2006-12-21 Matsushita Electric Ind Co Ltd Method for mounting ic tag
JP2007535743A (en) * 2004-04-30 2007-12-06 マイクロナス・ゲーエムベーハー Chip with power supply

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000134196A (en) * 1990-11-16 2000-05-12 General Instr Corp Terminal update system to keep maintain communications network
JPH08115267A (en) * 1994-10-19 1996-05-07 Tech Res & Dev Inst Of Japan Def Agency Information secrecy mechanism
WO1998053402A1 (en) * 1997-05-19 1998-11-26 Rohm Co., Ltd. Ic card and ic chip module
US6802008B1 (en) 1997-05-19 2004-10-05 Rohm Co., Ltd. IC card and IC chip module
US7003678B2 (en) 1997-05-19 2006-02-21 Rohm Co., Ltd. IC card and IC chip module
US6433927B1 (en) * 1999-12-02 2002-08-13 Jds Uniphase Inc. Low cost amplifier using bulk optics
JP2007535743A (en) * 2004-04-30 2007-12-06 マイクロナス・ゲーエムベーハー Chip with power supply
JP2006343844A (en) * 2005-06-07 2006-12-21 Matsushita Electric Ind Co Ltd Method for mounting ic tag

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