JPH0266949A - Charge-transfer device - Google Patents

Abstract

PURPOSE:To make it possible to reduce the resistance of a gate electrode without increasing the thickness of the entire gate electrode by composing the first and second gate electrode layers of a CCD of double-layer films of a polysilicon film and a silicon nitride film. CONSTITUTION:An N<-> impurity layer 2 is formed in a P-type silicon substrate 1. Then, a silicon dioxide film 3 and a polysilicon film 4 are deposited on the surface of the substrate 1. A silicon nitride film 19 is further deposited. Resist 8 is machined into a specified pattern. The silicon nitride film 19, the polysilicon film 4 and the silicon dioxide film 3 at a part where the resist 8 is not applied are removed. Thus a first gate electrode layer is formed. Then, the surface of the N<-> impurity layer 2 is oxidized, and a silicon dioxide film 5 is formed. A polysilicon film 6 and a silicon nitride film 22 are deposited by a CVD method. Resist 9 is machined into a specified pattern on the nitride film 22. The upper part of the first gate electrode layer is removed. With the resist 9 as a mask, the silicon nitride film 22 and the polysilicon film 6 are selectively removed,and a second gate electrode layer is formed.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a charge transfer device (hereinafter referred to as COD), and particularly relates to a COD in which the resistance of electrodes is reduced and the level difference on the substrate surface is reduced. .

[Prior art] Figure 3 is a solid! FIG. 2 is a block diagram of an ffJ element. Referring to FIG. 3, the solid-state image sensor includes a plurality of pixels 10 arranged to generate image signals, a vertical transfer CCD 11 for vertically transferring image signals received by the pixels 10, and a vertical transfer CCD 11 for vertically transferring image signals received by the pixels 10. It includes an Iζth vertical shift register 13 for optically generating a signal for transferring an image signal by the CCD 11, and a horizontal transfer CCD 14 for horizontally transferring the image signal carried by the vertical transfer CCD 11. FIG. 4 is a sectional view of a portion indicated by iv-1v in FIG. 3, and corresponds to a schematic sectional view of the vertical transfer COD.

Referring to FIG. 4, the vertical transfer CCD 11 includes a P-type semiconductor substrate 1, an N-impurity layer 2 formed on the P-type semiconductor substrate 1, and a gate insulating film 5 on the N-impurity layer 2. A first layer gate electrode 16.16' is formed through the first layer gate electrode 16.16', and a second layer gate electrode 17.17' is formed between the plurality of first layer gate electrodes 16.16'. The conventional two-layer drive COD shown in FIG.
and the second layer gate electrode 17' are connected to the wiring φ,
The first layer gate electrode 16 and the second layer gate electrode 17 are connected to the wiring φ2. φ5. φ2 is a clock signal line for driving the charge transfer element.

Next, the operation will be explained with reference to FIG.

FIG. 5 is a potential diagram of the semiconductor substrate under the gate insulating film corresponding to FIG. 4. To determine the charge transfer direction, two gate voltages # driven by the same clock φ are used.
A difference in potential is provided between A16' and A17'. FIG. 5(a) is a diagram showing the arrangement of gate electrodes. In Fig. 5(b), φ is I HI+, φ2 is “L”
is the potential of the combination of 1-electrode 16'
The potential below is the lowest, and the signal charge 18 is accumulated here. Next, φ1 is r I n, φ2 is 'H
5(C) shows the potential in the case of ``.'' In this state, the potential under the gate electrode 16 is the lowest.

By applying two clocks φ1 and φ2 that are 1800 times different from each other to the gate voltage 4, the clocks shown in FIG. 5 (b>, (C)
As shown in , the areas with low potential (wells) move sequentially. Since the signal charge 18 is accumulated in this potential well, it is transferred as shown in FIGS. 5(b) and 5(c).

Figures 6A to 6 are cross-sectional views showing a conventional COD manufacturing method. The manufacturing process will be described below with reference to FIGS. 6A to 6. First, N-
Impurity ll12 is formed (FIG. 6A). Next, board 1
Silicon dioxide # by oxidizing the surface! A3 is formed, and a polysilicon film 4 is deposited thereon by the CVD method (sixth
Figure B). Next, a resist 8 is applied onto the polysilicon film 4, and the resist 8 is processed into a predetermined pattern through a photolithography process (FIG. 6C). Then, using the resist as a mask, the polysilicon film 4 is etched and removed (FIG. 6D), and the silicon oxide film 3 under this removed polysilicon film 4 is etched and removed using the same resist 8 as a mask. (Figure 6E). Thereafter, a silicon dioxide film 5 is formed by oxidation (FIG. 6F), and then a second layer polysilicon film 6 is deposited by CVD (FIG. 6G). Next, a resist 9 is applied and a photolithography process is performed to process the resist 9 into a predetermined pattern.
Using this as a mask, polysilicon film 6 is selectively removed by etching (FIG. 61). Then, the silicon dioxide film 5 on the polysilicon film 4 is removed (FIG. 6J), and then oxidized to form the glabella insulating film 7 (FIG. 6).

After that, move on to the post-process.

FIG. 7 is a sectional view of the portion indicated by the Vff-■ line in FIG. 3. Referring to FIG. 7, each vertical transfer CCD 11A to 1
1C is separated by a field oxide film 25. The charge transfer potential from the vertical shift register 13 is transferred to each vertical transfer CCD 11A via the polysilicon film 4.
, 11B, and 11C. Therefore, if the resistance value of the polysilicon film 4 is large, the potential for charge transfer at the same time will be different between point A near the vertical shift register and eight points far away.

FIG. 8 is a diagram showing the relationship between time and potential on the horizontal transfer CCD. Referring to Fig. 8, the clock voltage at both ends of the horizontal transfer CCD m pole (points A and 8 in Fig. 3) rises approximately 20 ns after voltage application at the closest point A. On the other hand, at the farthest point B, it takes about 170 ns. That is, it can be seen that the farthest point B is delayed from the nearest point A by 150 ns or more.

[Problems to be Solved by the Invention] Conventional CODs have a structure as shown in the sixth figure and are manufactured through the steps described above. The drawback is that the film becomes thin due to oxidation, making it impossible to obtain the desired low sheet resistance. For example, in the case of a solid-state imaging device as shown in FIG. 3, the potential of the vertical transfer COD is transmitted from the vertical shift register 13 outside the image area 12 via the contact 15, so the polysilicon film 4.6 forming the electrode When the resistance becomes large, a delay as shown in FIG. 8 occurs before a predetermined potential is applied to the COD electrode at the other end. Furthermore, if the thickness of the polysilicon film is made thicker by taking into account the film thickness created when forming the polysilicon film 4.6, etching becomes difficult at the stepped portion of the film thickness, and the step becomes larger. There was a drawback that coverage deteriorated during the formation of the upper layer film in a later step, and the insulation and conductivity of the upper layer film deteriorated. These drawbacks have tended to become more significant as the COD has become more densely populated (approximately 2 million pixels or more).

The present invention has been made to solve the above-mentioned problems, and aims to increase the WA thickness of the entire gate power supply section, which is represented by the sum of the polysilicon film and the insulating film formed thereon. C, which can reduce the resistance of the gate electrode without
The purpose is to provide OD.

[Means for Solving the Problems] A COD according to the present invention includes a polysilicon film having a predetermined resistance value that becomes a transfer gate voltage, and an insulating film formed on the polysilicon film made of a silicon nitride film. .

[Operation] Since the insulating film formed on the polysilicon film includes a silicon nitride film, the insulating film is not formed by oxidation of the polysilicon. The thickness of the polysilicon layer as a conductive layer does not decrease as in the conventional case. Therefore, sheet resistance does not increase. Furthermore, since the insulation properties of the silicon nitride film are greater than those of the silicon oxide film, the thickness of the gate electrode portion as a whole can be reduced.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1st
The figure is a sectional view of a COD showing an embodiment according to the present invention. With reference to FIG. 1, the COD according to the present invention is P
type silicon substrate 1, an N- impurity layer 2 formed on the P-type silicon substrate 1, a silicon dioxide film 5 which is an insulating film formed on the N- impurity layer 2, and a silicon dioxide film 5 formed on the silicon dioxide film 5. The polysilicon WA4, which becomes the first layer gate electrode, is formed at intervals, and the polysilicon WA4 is formed on the region where the first layer gate electrode 4 is not formed and on the end opposite to the adjacent first layer gate electrode. An insulating film made of a silicon nitride film 22 is provided on the polysilicon film 4 that becomes the first layer gate electrode and the polysilicon film 6 that becomes the second layer gate electrode. It is formed.

Since the COD according to the present invention includes the above, the thickness of the insulating film can be reduced relative to the thickness of the polysilicon film having a predetermined resistance value. As a result, it is possible to provide a COD in which the resistance of the gate electrode <G can be lowered without increasing the film thickness of the gate electrode portion as a whole.

2A to 2H and FIG. 1 are C according to the present invention.
It is a figure which shows the manufacturing method of OD step by step. In the drawings, the same or equivalent parts as in FIGS. 6A to 6 are designated by the same reference numerals. The manufacturing process will be explained below with reference to the drawings. First, an N- impurity layer 2 is formed in a P-type silicon substrate 1 (FIG. 2A). Next, the surface of the substrate 1 is oxidized to form a silicon dioxide film 3, and a polysilicon film 4 is deposited thereon by the CVD method (FIG. 2B). Furthermore, silicon nitride WA 19 is deposited by the CVD method (FIG. 2B). figure)
. Then, a resist]-8 is applied, and the resist 8 is processed into a predetermined pattern through a photolithography process (FIG. 2D).

Next, the silicon nitride film 19, the polysilicon film 4, and the silicon dioxide film 3 on which the resist 8 is not applied are removed to form a first layer gate electrode (FIG. 2E).

Next, the surface of the N- impurity layer 2 is oxidized to form a silicon dioxide film 5 (FIG. 2F).

Next, a polysilicon film 6 is deposited by the CVD method, and a silicon nitride film 22 is further deposited by the CVD method (FIG. 2G). Then, a resist 9 is applied on this nitride film 22, and the resist 9 is processed into a predetermined pattern through a photolithography process, and the upper part of the first layer gate electrode is removed (Figure 2H).
. Using resist 9 as a mask, silicon nitride film 22 and polysilicon WA 6 are selectively removed to form second layer gate electrodes 4 - (FIG. 1).

In this way, since the polysilicon film of the first and second layer gate electrodes is covered with a nitride film to form a 21-layer structure, the polysilicon film is not oxidized. As a result, there is no increase in the resistance of Sea 1 due to oxidation of the polysilicon film in the oxidation process. For example, in order to obtain a sheet resistance of 20 Ω/hole, it would have been necessary to deposit polysilicon to a thickness of about 600 OA, taking into account the reduction in film thickness due to oxidation in the post-process, but this invention According to the report, the polysilicon H9'G is about 3,500 people, and the upper silicon nitride film is about 500 people.
Since 1 person is enough, the total current is only about 4000A. There are fewer steps than before, making it easier to process in post-processes. Therefore, forming a CCD cell using the method of this embodiment is advantageous in the production of future high-density image elements.

[Effect of the invention] As explained above, according to this invention, the first COD
and v5 To provide a COD in which the resistance of the gate electrode can be reduced without increasing the thickness of the entire gate electrode part, since the two-layer gate electrode is composed of a two-layer film of a polysilicon film and a silicon nitride film. Can be done.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a COD showing an embodiment according to the present invention, and FIGS. 2A to 2H are a cross-sectional view of a COD according to the present invention.
3 is a block diagram of a solid-state image transfer device, FIG. 4 is a cross-sectional view of the portion indicated by IV-IV in FIG. 3, and FIG. is the fourth
6A to 6 are cross-sectional views showing a conventional COD manufacturing method, and FIG. 7 is a potential diagram of a semiconductor substrate under a gate insulating film corresponding to the figure, and FIG. 8 is a cross-sectional view of the portion indicated by the line, and FIG. 8 is a diagram showing the relationship between time and potential on the horizontal transfer CCD. 1 is a P-type silicon substrate, 2 is an N- impurity layer, 3 is a silicon dioxide film, 4 is a polysilicon film, 5 is a silicon dioxide film, 6 is a polysilicon film, 7 is an insulating film between the eyebrows, 8.9 is a resist, 10 is a pixel, 11 is a vertical transfer COD, 12 is an image area, 13 is a vertical shift register, 14 is a horizontal transfer COD, and 15 is a contact. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Figure 1

Claims (1)

[Scope of Claims] A semiconductor substrate having a main surface and having a predetermined impurity concentration of a first conductivity type, and an impurity having a predetermined impurity concentration of a second conductivity type formed on the main surface of the semiconductor substrate. a plurality of first polysilicon layers formed on the impurity layer in a predetermined direction with an insulating film interposed therebetween and arranged in alignment at intervals, each of the first polysilicon layers; The silicon layer has a main surface and one and the other end in the aligned direction, and is formed on the main surface of the first polysilicon layer and covering at least the one and the other end. a second polysilicon layer formed on the impurity layer and on the region where the first polysilicon layer is not formed, with an insulating film interposed therebetween, and on the silicon nitride film; and a silicon nitride film formed on the second polysilicon layer.