JPH02260542A - Manufacture of charge transfer element - Google Patents

Abstract

PURPOSE:To eliminate potential difference between gate electrodes by performing only one thermal oxidation process for forming an insulator which is to be included between a semiconductor substrate and a gate electrode. CONSTITUTION:A silicon dioxide film 3 which becomes a first insulating film is formed by oxidizing the surface of a P-type silicon substrate 1 and a gate insulating film is formed in three-layer structure by a silicon dioxide film 3 by this thermal oxidation, a silicon nitriding film 11 by the CVD method, and silicon dioxide films 10 and 12, thus achieving only one oxidation process. Polysilicon patterns 4a and 6a thus obtained are placed alternately and they become each gate electrode of charge transfer element. Then, no difference occurs in the impurities concentration in an N<-> impurities layer 2 below a first-layer gate electrode 4a and below a second-layer gate electrode 6a. Therefore, no difference occurs in the potential below each gate electrode in the silicon substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a charge transfer device (hereinafter also referred to as a CCD).

[Conventional technology]

FIG. 3 is a plan view showing a schematic configuration of the solid-state imaging device. That is, this solid-state imaging device has, as its constituent elements, a plurality of pixels 14 that are arranged in a matrix to form an image area 13 in order to generate image signals, and an image signal generated by the pixels 14 that is arranged in a matrix to form an image area 13. The data is transferred by a vertical transfer CCD 15 for transferring in the vertical direction (vertical direction in FIG. 3), a vertical shift register 16 for generating a clock signal for driving this vertical transfer CCD 15, and a vertical transfer CCD 1-5. It includes a horizontal transfer CCD 17 for sequentially transferring image signals in the horizontal direction (horizontal direction in FIG. 3).

FIG. 4 is a cross-sectional view taken along the line IV--IV in FIG. 3, that is, a cross-sectional view showing a schematic configuration of the vertical transfer CCD 15. That is, this vertical transfer CCD 15 has, as its constituent elements, a P-type semiconductor substrate 1, an N impurity layer 2 formed on the surface layer of the P-type semiconductor substrate 1, and an insulating film 5 formed on the N impurity layer 2. A plurality of first layer gate electrodes 1
8.18' and a plurality of second layer gate electrodes 19.19' formed between these first layer gate electrodes 18.18'. Note that the upper surface of the second layer gate electrode 19, 19' is covered with an insulating film 7.

In FIG. 4, signal lines 20 and 21 are wirings for transmitting clock signals φ and φ2 for driving the vertical transfer CCD 15, respectively, and the first layer gate electrode 18 and the second layer gate electrode 19 are The first layer gate electrode 18' and the second layer gate electrode 19' are connected to the other signal line 21.

FIGS. 5(a) to 5(k) show the vertical transfer CCD 15 (7).
) FIG. 3 is a cross-sectional view showing each step in a conventional manufacturing method.

That is, in this manufacturing method, the N impurity layer 2 is first formed on the entire surface of the P-type silicon substrate 1 (the fifth
Figure (a)).

Next, by oxidizing the surface of the P-type silicon substrate 1, a silicon dioxide film 3 that will become a gate insulating film is formed.
Furthermore, a polysilicon film 4 is deposited on the silicon dioxide film 3 by the CVD method (FIG. 5(b)).

Next, a resist is applied onto the polysilicon film 4, and the resist is processed into a plurality of resist patterns 8 arranged at predetermined intervals through a photolithography process (
Figure 5(C)).

Next, using the resist pattern 8 as a mask, the polysilicon film 4 is selectively removed by etching to form a polysilicon pattern 4a (FIG. 5(d)).
Furthermore, the silicon dioxide film 3 below the removed polysilicon film 4 is also selectively etched and removed (
Figure 5(e)). The thus obtained polysilicon pattern 4a serves as the first layer gate electrode 16, 16'.
becomes.

Thereafter, oxidation is performed over the removed region of the silicon dioxide film 3 and the entire surface of the polysilicon pattern 4a, thereby forming a silicon dioxide film 5 which becomes an insulating film (FIG. 5 ()), and then the silicon dioxide film A second layer of polysilicon film 6 is deposited on 5 by the CVD method (FIG. 5(g)).

Next, a resist is applied onto the polysilicon film 6, and the resist is processed into a plurality of resist patterns 9 arranged at predetermined intervals through a photolithography process (
Figure 5(h)). That is, these resist patterns 9 are located at intermediate positions between mutually adjacent polysilicon patterns 4a, and are located at intermediate positions between adjacent polysilicon patterns 4a.
are arranged so that a portion of each of them overlaps.

Next, in the same manner, the second layer polysilicon film 6 is selectively removed by etching to form a polysilicon pattern 6a (FIG. 5 (■)).

The polysilicon pattern 6a thus obtained becomes the second layer gate electrode 17, 17' described above.

Next, using the polysilicon pattern 6a as a mask, the silicon dioxide film 5 on the first layer polysilicon pattern 4a is
is selectively removed (FIG. 5(j)), and then the removed area of the silicon dioxide film 5 (exposed part of the first layer polysilicon pattern 4a) and the second layer polysilicon pattern 6 are removed.
Oxidation is performed over the entire surface a, thereby forming an interlayer insulating film 7 (FIG. 5(k)). After that, post-processing is performed.

6(a) to (C) are the vertical transfer CCD 1 shown in FIG.
6(a) is a cross-sectional view of the vertical transfer C0D13, and FIG. (b) and (c) each gate electrode 1
8, 19. It is a schematic diagram showing the states of potentials corresponding to 18' and 19'. This figure 6 (a) to (c)
The operation of the vertical transfer CCD 15 will be described below with reference to FIG.

In order to determine the direction of charge transfer in the vertical transfer CCD 15, there are two gate electrodes 18 and 19, one driven by the clock signal φ1, and the other gate electrode 18' driven by the clock signal φ2. , 19' are configured so that a difference in potential occurs between them.

Furthermore, the two clock signals φ and φ2 have phases different from each other by 180°, and one of the clock signals φ
When the clock signal φ2 is H and the other clock signal φ2 is L, the potential under the gate electrode 18 becomes the lowest and the signal charge 22 is accumulated there, as shown in FIG. 6(b). Next, clock signal φ1 is changed to L1 clock signal φ2.
Assuming that H is the gate electrode 1 as shown in FIG. 6(e),
The potential below 8' becomes the lowest, and the signal charge 22 is transferred and accumulated there as shown by the arrow.

By repeating the drive using the above clock signals φ and φ2, the area where the potential is lowest (
(potential wells) move sequentially, and thereby the signal charges 22 are sequentially transferred in the arrangement direction of the gate electrodes 18, 19, 18', 19'.

Note that the clock signals φ 1 and φ 2 are transmitted from the vertical shift register 6 shown in FIG.
．． 18' and 19', but the signal line 20
．． The specific structure of 21 is shown in a sectional view in FIG. That is, FIG. 7 is a cross-sectional view taken along the line ■--■ in FIG.

Then, the clock signal φ from the vertical shift register 6
, φ2 are transmitted to each vertical transfer CCD 15A to 15C via polysilicon patterns 4a and 6a (FIG. 7 shows a portion of polysilicon pattern 4a corresponding to first layer gate electrode 18, 18'). . That is, the main parts of the polysilicon patterns 4a, 6a function as gate electrodes 18.18', 19.19', and the other parts function as the above-mentioned signal lines 20.21.

[Problem to be solved by the invention]

However, in the conventional method for manufacturing a charge transfer device described above, the step of forming an insulating film (silicon dioxide film 5) shown in FIG. 5(f') and the step of forming an interlayer insulating film 7 shown in FIG. In the step of forming gate electrodes 18, 19.1
8', 19' and the polysilicon patterns 4a and 6a that will become the signal lines 20 and 21 are oxidized and the actual polysilicon layer thickness becomes thinner, so that the signal lines 20 and 21 are not as low as the intended thickness. The problem was that resistance could not be obtained.

For example, in FIG. 7, when the resistance value of the polysilicon pattern 4a increases, the
At point B, which is farther away than point B, there is a delay in the transmission of the clock signals .phi.1 and .phi.2, and as a result, there is a difference in potential for charge transfer at the same time between point A and point B.

FIG. 8 is a waveform diagram showing the rising waveform of the clock signal (voltage) at the points A and B. As shown in the figure, at the closest point A, the waveform rises approximately 20 ns after the clock signal is applied, while at the farthest point B, it takes approximately 170 ns to rise.
It took n seconds.

That is, it can be seen that the farthest point B is delayed from the nearest point A by 150 ns or more.

On the other hand, in order to solve the above problem, for example, if the thickness of the polysilicon film 4.6 is increased by taking into account the thickness of the film that is oxidized when forming the polysilicon patterns 4a and 6a, the thickness of the polysilicon film 4.6 is increased, especially at the stepped portions. Etching becomes difficult and the first
layer gate electrode 18°18' and second layer gate electrode 19.1
The difference in level between the layers 9' becomes large, resulting in poor coverage during the formation of an upper layer film in a subsequent process, and the insulation and conductivity of the upper layer film are also deteriorated. In other words, if an attempt is made to lower the sheet resistance of the gate electrode, the film thickness of the entire gate electrode portion will increase, leading to deterioration of its characteristics. The impact of these problems is due to the increase in pixel density of solid-state imaging devices (
(approximately 2 million pixels or more), the size increases.

Furthermore, in the conventional manufacturing method described above, the P-type semiconductor substrate 1
Of the N- impurity layer 2, the portion under the first layer polysilicon pattern 4a is oxidized only once in the step shown in FIG. The portion under the silicon pattern 6a will be oxidized twice, in the step of FIG. 5(b) and the step of FIG. 5(f). As a result, the impurity concentration of the N- impurity layer 2 is
There was also a problem that the potential was different between the first layer gate electrode 18.18' and the second layer gate electrode 19.19', making it difficult to control charge transfer. .

This invention was made to solve these problems, and it is possible to reduce the resistance of the gate electrode without increasing the thickness of the entire gate electrode part, and to eliminate the potential difference between the gate electrodes. The purpose of this invention is to obtain a method for manufacturing a charge transfer device that can be used.

[Means to solve the problem]

A method for manufacturing a charge transfer device according to the present invention includes the steps of forming an impurity layer of a second conductivity type on the entire surface of a semiconductor substrate of a first conductivity type, and forming a first insulating layer on the impurity layer by a thermal oxidation method. forming a film, forming an etching stopper thin film on the first insulating film, forming a second insulating film on the etching stopper thin film by CVD, and forming a conductive film on the etching stopper thin film. forming a plurality of first gate electrodes arranged at intervals on the second insulating film; and a region of the second insulating film exposed from between the first gate electrodes. After etching and removing the second insulating film, a third insulating film covering the removed area of the second insulating film and the entire surface of the first gate electrode is etched by CVD.
a step of forming a plurality of second gate electrodes by method D, and a plurality of second gate electrodes made of conductive films and arranged at intervals, on the third insulating film and alternately with the first gate electrodes; The method includes a step of forming the wafer at a position where the wafer is formed.

[Effect]

In this invention, since thermal oxidation is required only once to form the insulating film interposed between the semiconductor substrate and the gate electrode, there is no difference in impurity concentration in the impurity layer of the semiconductor substrate. There is no difference between the potentials under the gate electrode and the second gate electrode.

Furthermore, since no oxidation process is introduced during the formation of the second gate electrode, the actual conductor film thickness of the first gate electrode will not be reduced by oxidation, and the sheet resistance of the gate electrode will therefore be reduced. be done.

〔Example〕

FIGS. 1(a) to 1(1) are cross-sectional views showing one embodiment of each step in the method for manufacturing a charge transfer device according to the present invention. In this figure, the same or equivalent parts as in FIGS. 5(a) to 5(k) are designated by the same reference numerals.

The manufacturing process will be described below with reference to FIGS. 1(a) to (1).

First, an N″″ impurity layer 2 is formed on the entire surface of a P-type silicon substrate 1.
is formed (Fig. 1(a)).

Next, by oxidizing the surface of the P-type silicon substrate 1, a silicon dioxide film 3, which becomes a first insulating film, is formed.
Next, a silicon nitride film 11, which will serve as an etching stopper in a subsequent process, is deposited thereon by CVD.
Furthermore, a silicon dioxide film 12 which becomes a second insulating film is deposited on the silicon nitride film 11 by the same CVD method, and a polysilicon film 4 is deposited on the silicon dioxide film 12 by the same CVD method. (Figure 1 (
b)).

Next, a resist is applied onto the polysilicon film 4, and the resist is processed into a plurality of resist patterns 8 arranged at predetermined intervals from each other through a photolithography process.

(Figure 1 (C)).

Next, using the resist pattern 8 as a mask, the polysilicon film 4 is selectively removed by etching to form a polysilicon pattern 4a (FIG. 1(d)).

Furthermore, the silicon dioxide film 12 under the removed polysilicon film 4 is also etched in the same way, thereby selectively removing the silicon dioxide film 12 (FIG. 1(e)).
).

Next, a third insulating film of silicon dioxide 1l110 is deposited over the removed region of the silicon dioxide film 12 and the entire surface of the polysilicon pattern 4a by the CVD method, and a second layer of silicon dioxide 1l110 is further formed on the silicon dioxide film 10. A polysilicon film 6 is deposited by CVD method (
Figure 1(r)).

Furthermore, a resist is applied on the polysilicon@6,
The resist is processed into a plurality of resist patterns (turns 9) arranged at a predetermined distance from each other through a photolithography process (FIG. 1(g)).In other words, these resist patterns 9 are It is arranged at an intermediate position between the polysilicon patterns 4a and at a position partially overlapping each of the adjacent polysilicon patterns 4a.

Next, using the resist pattern 9 as a mask, the second layer of polysilicon film 6 is selectively removed by etching to form a polysilicon pattern 6a, and then the first layer of polysilicon and the silicon dioxide film on turn 4a are removed. 10 is also selectively removed by similar etching (
Figure 1 (h)).

Next, a silicon dioxide film 7, which will become an insulating film between the eyebrows, is deposited by CVD over the removed region of the silicon dioxide film 10 (the exposed part of the first-layer polysilicon pattern 4a) and the entire surface of the second-layer polysilicon pattern 6a. (Figure 1 (1)).

The polysilicon pattern 4a obtained in this way
, 6a are arranged alternately and serve as each gate electrode of the charge transfer element. Each of these gate electrodes is made of a silicon dioxide film 7 deposited by the CVD method.
10.12.

In this manufacturing method, silicon dioxide film 3 is formed by thermal oxidation.
Since the gate insulating film is composed of a three-layer structure of silicon nitride film 11 and silicon dioxide 111110.12 by the CVD method, the oxidation process is only performed once, and the oxidation process is performed only once, and the oxidation process is performed only once. There is no difference in the impurity concentration in the N″″ impurity layer 2 under the second layer gate electrode (polysilicon pattern 6g). Therefore, there is no difference in the potential under each gate electrode on the silicon substrate 1.

FIG. 2 shows the 1. The film thickness d2 of the silicon nitride film 11 and the silicon dioxide film 12,
3 is a graph showing the relationship of film thickness distribution with each film thickness d and d of No. 3. As is clear from FIG. 2, in the gate insulating film of the three-layer structure, for example, the thickness d2 of the silicon nitride film 11 is 200, and the thickness d2 of the silicon dioxide film 3 is 120.
If +d3) is 900 people, the capacity will be the same as above, but the total thickness of the gate insulating film in this case will be 1100 people, which is almost the same as the gate insulating film made of a single layer of silicon dioxide film. It can be kept thick. Furthermore, since the silicon nitride film 11 in this case is formed as an etching stopper when etching and soching the upper silicon dioxide film 12, its film thickness d2 is sufficient for about 200 people to deposit, and there is no problem.

Further, as described above, since each gate electrode is covered with the silicon dioxide film 7, 10.12 deposited by the CVD method, the silicon dioxide film 7, 10.
The gate electrodes, that is, the polysilicon patterns 4a and 6a, are not oxidized with the formation of the gate electrode 12, and therefore the sheet resistance of the gate electrodes does not increase due to oxidation. For example, in order to suppress the sheet resistance to 20Ω/hole, conventionally the resistance was approximately 60Ω, taking into account the reduction in film thickness due to oxidation in the post-process.
In this example, the thickness of the polysilicon film is 350 mm.
The thickness of the silicon dioxide film covering the top of the silicon dioxide film is about 500, so the total thickness is only about 6,000. Therefore, the step difference at the gate electrode portion is also smaller than before, and processing in subsequent steps becomes easier. Note that although the above embodiment was applied to a two-phase CCD, a CCD of three or more phases can also be manufactured by the same method.

〔Effect of the invention〕

As described above, according to the present invention, the thermal oxidation step is completed only once in forming the insulating film interposed between the semiconductor substrate and the gate electrode, so that the impurity concentration in the impurity layer of the semiconductor substrate is reduced. Therefore, it is possible to eliminate potential differences between the gate electrodes.

In addition, since the oxidation process is not carried out after the formation of the first gate electrode, the actual conductor film thickness of the gate electrode does not decrease due to oxidation, and therefore the film thickness of the entire gate electrode portion can be increased. The resistance of the gate voltage can be reduced without any problems.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the steps of an embodiment of the method for manufacturing a charge transfer device according to the present invention, and FIG. 2 is a graph showing the relationship between film thickness distribution in a gate insulating film with a three-layer structure obtained by the manufacturing method. , FIG. 3 is a schematic diagram showing a schematic planar configuration of a solid-state imaging device, FIG. 4 is a sectional view taken along the line IV-IV in FIG. 3, and FIG. 5 shows the steps of a conventional method for manufacturing a charge transfer device. 6 is an explanatory diagram showing the state of potential under the gate electrode of the charge transfer element, and FIG.
8 is a waveform diagram for explaining the delay in transmitting the clock signal to the charge transfer element. In the figure, 1 is a P-type silicon substrate, 2 is an N impurity layer,
3, 10.12 are silicon dioxide films, 4.6 is a polysilicon film, 4a and 6a are polysilicon patterns, and 11 is a silicon nitride film. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) a step of forming an impurity layer of a second conductivity type on one main surface of a semiconductor substrate of a first conductivity type; a step of forming a first insulating film on the impurity layer by a thermal oxidation method; a step of forming a thin film for etching stopper on the first insulating film; a step of forming a second insulating film on the thin film for etching stopper by a CVD method; forming a plurality of first gate electrodes arranged in a row on the second insulating film; and etching and removing a region of the second insulating film exposed from between the first gate electrodes. After that, the second
a step of forming a third insulating film covering the removed region of the insulating film and the entire surface of the first gate electrode by a CVD method; A method for manufacturing a charge transfer device, comprising the step of forming gate electrodes on the third insulating film at positions alternately arranged with the first gate electrodes.