JPH0266053U - - Google Patents

Info

Publication number
JPH0266053U
JPH0266053U JP14550888U JP14550888U JPH0266053U JP H0266053 U JPH0266053 U JP H0266053U JP 14550888 U JP14550888 U JP 14550888U JP 14550888 U JP14550888 U JP 14550888U JP H0266053 U JPH0266053 U JP H0266053U
Authority
JP
Japan
Prior art keywords
data
transmission path
sampling circuit
sampling
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14550888U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14550888U priority Critical patent/JPH0266053U/ja
Publication of JPH0266053U publication Critical patent/JPH0266053U/ja
Pending legal-status Critical Current

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Landscapes

  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例の主要部のブロツク
図、第２図は積分回路の回路図、第３図は第２図
の回路の各点の波形図である。 １……終端装置（ＤＣＥ）、２……端末装置（
ＤＴＥ）、３……ケーブル、１１，１２，２１，
２３……増幅器、１３，２２……Ｄ形のフリツプ
フロツプ回路（ＦＦＣ）、１４……積分回路、３
１，３２……インバータ回路、３３……抵抗器、
３４……コンデンサ、Ｓｄ……遅延タイミング信
号。 FIG. 1 is a block diagram of the main part of an embodiment of the present invention, FIG. 2 is a circuit diagram of an integrating circuit, and FIG. 3 is a waveform diagram at each point in the circuit of FIG. 1...Terminal equipment (DCE), 2...Terminal equipment (
DTE), 3...cable, 11, 12, 21,
23...Amplifier, 13, 22...D-type flip-flop circuit (FFC), 14...Integrator circuit, 3
1, 32... Inverter circuit, 33... Resistor,
34...Capacitor, Sd...Delay timing signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データ回線用の終端装置から伝送路を介して端
末装置に送出するタイミング信号に同期して前記
端末装置は送信データを送出し前記終端装置は前
記伝送路を介して前記送信データを受信し前記タ
イミング信号に従つてサンプリングしてデータの
送信を行うデータ通信装置のサンプリング回路に
おいて、前記終端装置の送出した前記タイミング
信号に対応して前記伝送路を介して送出される前
記送信データの遅延時間に応じてサンプリングの
時刻を変化させる手段を設けたことを特徴とする
データ通信装置のサンプリング回路。 The terminal device sends out transmission data in synchronization with a timing signal sent from a data line termination device to the terminal device via a transmission path, and the termination device receives the transmission data through the transmission path, and In a sampling circuit of a data communication device that transmits data by sampling in accordance with a signal, the transmission data is transmitted via the transmission path in response to the timing signal transmitted by the terminating device. 1. A sampling circuit for a data communication device, characterized in that the sampling circuit is provided with means for changing a sampling time.
JP14550888U 1988-11-07 1988-11-07 Pending JPH0266053U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14550888U JPH0266053U (en) 1988-11-07 1988-11-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14550888U JPH0266053U (en) 1988-11-07 1988-11-07

Publications (1)

Publication Number Publication Date
JPH0266053U true JPH0266053U (en) 1990-05-18

Family

ID=31414162

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14550888U Pending JPH0266053U (en) 1988-11-07 1988-11-07

Country Status (1)

Country Link
JP (1) JPH0266053U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0484530A (en) * 1990-07-27 1992-03-17 Mitsubishi Electric Corp Signal transmission method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0484530A (en) * 1990-07-27 1992-03-17 Mitsubishi Electric Corp Signal transmission method

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