JPH0264840A - Data transfer equipment - Google Patents

Abstract

PURPOSE:To stably transfer words between a central processing unit and plural peripheral equipments by using a data decision signal showing the decision of a high byte and a low byte. CONSTITUTION:A data decision circuit 13 transmits transmission data switched in a multiplexer 2 to a data bus 8 and transmits the data decision signal 14 to the peripheral equipments by generating the data decision signal 14 by a high/low switching signal 11 and controlling a buffer circuit 3. At that time, a byte switching timing circuit 5 transmits timings which transmission data decides in the high byte and the low byte to the peripheral equipments as data timing pulses 9. Thus, the data decision signal 14 is provided and the decision of data of the high byte and the low byte is instructed to the peripheral equipments. Thus, data is stably transferred between the central processing unit 1 and the peripheral equipments.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer device, and particularly to a data transfer device that stably performs word transfer between a central processing unit and a plurality of peripheral devices.

[Conventional technology] FIG. 2 is a block diagram of a conventional data transfer device.

In the figure, l is a central processing unit (CPU), 2 is a multiplexer, 3 and 7 are buffer circuits, 4 is a word byte identification circuit, 5 is a byte switching timing circuit, 6 is a latch circuit, and 8 is an 8-bit data bus. be.

In the above configuration, when the 16-bit central processing unit 1 performs byte access with a peripheral device, the word byte identification circuit 4 identifies a byte access and sends an identification signal to the byte switching timing circuit 5. When the byte switching timing circuit 5 receives this identification signal,
A switching signal is sent to the multiplexer 2 via the high/low switching signal line 11.

On the other hand, the multiplexer 2 switches the transmission data into a high byte and a low byte, and transmits the data to the 8-bit data bus 8 via the buffer circuit 3 in response to the two signals sent from the central processing unit 1 to the word byte identification circuit 4. Send to.

In this case, the byte switching timing circuit 5 outputs the timing at which the transmission data is determined as a high byte and a low byte, respectively, as a data timing pulse 9 to each peripheral device. Therefore, on the peripheral device side, the transmission data read by this data timing pulse 9 is hi-bye!・
and switch the low bite.

Now, when the peripheral device receives a write signal instructing the transfer direction, it latches the high byte and low byte from the central processing unit 1 using the established data timing pulse 9.

On the other hand, when receiving transmission data from each peripheral device, the word byte identification circuit 4 identifies word access and sends an identification signal to the byte switching timing circuit 5. When the byte switching timing circuit 5 receives the identification signal, it sends a latch pulse 1 to the latch circuit 6.
Send 2.

Then, the latch circuit 6 latches the first byte data sent via the 8-bit data bus 8. Then, along with the next byte data input to the buffer circuit 7 via the 8-bit data bus 8, it is taken in as a word into the central processing unit 1.

Conventional data transfer devices perform word transfer as described above.

[Problems to be solved] In the conventional data transfer device described above, if noise is generated from the buffer circuit when switching between the high byte and low byte of the transmission data, the write signal changes midway, so it is difficult for peripheral devices to There was a problem in that the high byte and low byte of the transmitted data could not be latched correctly.

Also, when the central processing unit reads data from a peripheral device, if noise occurs due to switching between high byte and low byte of data sent from the peripheral device, the read signal changes midway, causing the data to be sent correctly. There was a problem that the data could not be sent to the central processing unit.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a data transfer device that stably performs word transfer between a central processing unit and a plurality of peripheral devices.

[Means for solving the problem] In order to achieve the above object, the data transfer device of the present invention has the following features:
A CPU that performs word transfer, a multiplexer that switches and outputs word data into high byte and low byte when transmitting data by word transfer, and a multiplexer that latches the high byte that is continuously transferred when receiving data by word transfer. , a latch circuit that outputs the low byte data as word data to the CPU, a buffer circuit that temporarily stores input/output data, a word byte identification circuit that detects word access by the CPU, and this word byte identification circuit. When a word access is detected, a byte switching timing circuit controls the multiplexer and latch circuit to switch between high byte and low byte, and the high byte and low byte are switched according to the switching timing by this byte switching timing circuit. The configuration includes a data confirmation circuit that transmits and receives data when the data is confirmed.

In other words, the transmission data is switched between high byte and low byte in response to a word transfer command from the CPU, and when data is continuously transferred to a peripheral device, the high byte and low byte are switched in order to transfer data stably. A data confirmation signal is used to indicate confirmation.

Similarly, in order to stably transfer data from the peripheral device to the CPU, a data confirmation signal is used to instruct data transmission when the high byte and low byte from the peripheral device are confirmed.

[Example] Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 is a block diagram of a data transfer device according to an embodiment of the present invention. Note that parts common to or corresponding to those of the conventional example are denoted by the same reference numerals.

In the figure, 13 is a data confirmation circuit.

In the above configuration, when the 16-bit central processing unit 1 performs byte access with a peripheral device, the word byte identification circuit 4, the byte switching timing circuit 5, and the multiplexer 2 switch the transmission data into a high byte and a low byte and transmit the data. . This basic processing is unchanged from the conventional one.

However, the data confirmation circuit 13 creates the data confirmation signal 14 based on the high/low switching signal 11. By controlling the buffer circuit 3, the transmission data switched by the multiplexer 2 is sent to the 8-bit data bus 8, and the data confirmation signal 14 is sent to the peripheral device.

At this time, the byte switching timing circuit 5 sends the timing at which the transmission data is determined as a high byte and a low byte to each peripheral device as a data timing pulse 9.

On the other hand, each peripheral device uses the data confirmation signal 14 to enable the device side buffer circuit, and uses the data timing pulse 9 to take in transmission data and switch bytes.

On the other hand, when receiving transmission data from each peripheral device, the word byte identification circuit 4 identifies word access, and the byte switching timing circuit 5 sends a high/low switching signal 11 to the data confirmation circuit 13. do. Then, the data confirmation circuit 13 sends a data confirmation signal 14 to the peripheral device when the transmission data of the peripheral device is confirmed, and instructs the peripheral device to send the data to the 8-bit data bus 8. Thereafter, the latch circuit 6 and buffer circuit 7 receive the high byte and low byte in the same way as in the past, and when the subsequent data is determined, the central processing unit l
is imported as a word.

In this way, in this embodiment, when transferring data between the central processing unit and the peripheral device, the byte switching means switches the transmitted data between high byte and low byte in response to a word transfer command from the central processing unit. In order to stably send data to the peripheral device when continuously sending data to the peripheral device, a data confirmation signal is provided to instruct the peripheral device to confirm the high byte and low byte data.

Similarly, in response to a word transfer command from the central processing unit, the data supply means switches and receives data continuously transmitted from a peripheral device into high byte and low byte, and supplies the data to the central processing unit. In order to stably read data from the peripheral device, once the data is stable, a data confirmation signal is sent to the peripheral device to output the data.

[Effects of the Invention] As explained above, the present invention transmits transmission data from the CPU as a word, and also uses a multiplexer to switch the word into a high byte and a low byte and transmits it continuously. By using the data confirmation signal in data transfer (byte access) in which bit data is read out twice, it is possible to provide a data transfer device that stably transfers data between the CPU and peripheral devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data transfer device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional data transfer device. 1: Central processing unit 2: Multiplexer 3.7: Buffer 7 circuit 4: Word byte identification circuit 5: Byte switching timing circuit 6: Latch circuit 13: Data confirmation circuit

Claims (1)

[Claims] A CPU that performs word transfer, a multiplexer that switches and outputs word data into high byte and low byte when transmitting data by word transfer, and a multiplexer that latches the high byte that is continuously transferred when receiving data by word transfer. , a latch circuit that outputs the low byte data as word data to the CPU, a buffer circuit that temporarily stores input/output data, a word byte identification circuit that detects word access by the CPU, and this word byte identification circuit. When a word access is detected, a byte switching timing circuit controls the multiplexer and latch circuit to switch between high byte and low byte, and the high byte and low byte are switched according to the switching timing by this byte switching timing circuit. 1. A data transfer device comprising: a data confirmation circuit that transmits and receives data when data is confirmed.