JPH0263839A - Printer device - Google Patents

Abstract

PURPOSE:To correctly form a synchronous clock for serial printing image data by a method wherein a timing signal required for printing processing is superimposed on input serial image data to be outputted, and a signal is extracted from the image information signal with the timing signal superimposed. CONSTITUTION:Timing information for determining a synchronous timing with a printing part is superimposed on a video signal by a controller 15, and this superimposed image signal MVO is outputted to the printing part. Then, a phase detection circuit 2 detects the phase of the video signal, and based on the detected phase an image data forming circuit 3 forms image data to be transferred to the printing part. On the other hand, in parallel to said processing the timing information is extracted from the superimposed image signal inputted to a timing extraction circuit 4, and a timing generation circuit 5 generates a synchronous timing signal for processing the image data generated by the image data forming circuit 3. On this synchronous timing signal, the printing part starts the printing of the image data. In this manner, a synchronous timing for the transferred serial image data is correctly determined.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a printer device that performs printing based on an input asynchronous serial video signal.

[Conventional technology]

Conventional printer devices perform print processing by processing serially input video signals synchronously or asynchronously.

For example, when a synchronized clock for video data is provided as a video interface from the controller main body, which is an image signal source, and printing processing is performed based on the synchronized clock, and when the printer main body side does not have a synchronized clock, video data sampling, etc. In some cases, a timing signal for video data is created to perform printing processing.

[Problem to be solved by the invention]

However, in the former case, it is necessary to permanently install a line dedicated to the synchronization clock, which increases the number of interface lines between the host side and the printer side.As the length of the interface cable increases, the delay difference and waveform between the timing clock and video data increases. There was a problem that the synchronization timing deviated from the normal synchronization timing due to distortion, etc.

In addition, in the latter case, the phase of the timing clock created in the printer device is corrected at the color change point of the image data, so if the image data is continuous black or white, there is no change point, so timing correction is not required. Not done.

Furthermore, the circuit configuration for performing timing correction becomes complicated, leading to problems such as increased circuit cost.

The present invention was made to solve the above problems, and outputs a timing signal necessary for printing processing while superimposing it on input serial image data, thereby producing an image information signal on which the timing signal is superimposed. It is an object of the present invention to provide a printer device that can accurately create a synchronization clock for serial print image data by extracting a signal from the serial print image data.

[Means to solve the problem]

The printer device according to the present invention includes a superimposing means for creating a superimposed image signal by superimposing timing information for determining synchronization timing with a printing section on a video signal, and a video signal from the superimposed image signal created by the superimposing means. a phase detection means for detecting the phase of the signal; an image data creation means for creating image data to be transferred to the printing section based on the phase of the video signal detected by the phase detection means; and timing signal creation means for creating a synchronization timing signal for processing the image data extracted and created by the image data creation means.

[Effect]

In this invention, when the superimposing means superimposes the timing information for determining the synchronization timing with the printing section on the video signal and outputs the superimposed image signal to the printing section, the phase detection means detects the timing information in the superimposed image signal. The phase of the video signal is detected from the phase of the video signal, and the image data creation means creates image data to be transferred to the printing section based on the detected phase.

Meanwhile, in parallel with this image data creation process, a timing signal creation means extracts timing information from the input superimposed image signal and creates a synchronous timing signal for processing the image data created by the image data creation means. Then, the printing section starts printing the image data in response to this synchronization timing signal.

[Embodiment] FIG. 1 is a block diagram illustrating the configuration of a printer device showing an embodiment of the present invention, and corresponds to an example of the configuration of a thermal printer device having a thermal head, for example.

In this figure, 1 is a buffer element, and controller 1
The superimposed image signal MV○ outputted from the image output boat VID of No. 5 is transferred to the image information processing section 16. The image information processing section 16 includes a phase detection circuit 2, an image data creation circuit 3. A controller 15, which is composed of a timing extraction circuit 4, a timing generation circuit 5, etc., and also serves as a superimposing means, superimposes timing information on the video signal VDO to determine the synchronization timing with the printing section, and generates a superimposed image signal on the printing section. When MVO is output, the phase detection circuit 2 serving as a phase detection means detects the video signal VDO from the superimposed image signal MVo.
Based on the detected phase, an image data creation circuit 3 serving as an image data creation means creates image data VIDEO (binary image data) to be transferred to the printing unit.

On the other hand, in parallel with this image data creation process, a timing signal creation means (consisting of a timing extraction circuit 4 and a timing creation circuit 5) inputs a superimposed image signal MV.
Image data creation circuit 3 extracting timing information from O
A synchronization timing signal for processing the image data created by the above is created, and the printing section starts printing the image data in response to this synchronization timing signal. In addition, the printing part is a thermal head 9. Driver circuit 10. It is composed of a shift register circuit 11 and the like.

6 is a video counter circuit that counts the synchronization timing signal VCLK output from the timing generation circuit 5 by a predetermined number based on the main scanning synchronization signal (horizontal synchronization signal) BDS, and after the count ends, outputs a count-up signal (lip carry). It is output to the shift register circuit 11. 7 is a line counter circuit that counts the horizontal synchronizing signal BDS sent from the boat BD of the controller 15 via the buffer element 1, and after the count-up is completed, outputs a count-up signal to the AND gate 8, and counts up the count-up signal for one image data. Stops the printing process.

Reference numeral 12 denotes an interface circuit that mutually interfaces printing control information from the controller 15 to a control circuit 13 serving as a printer control unit via a parallel interface bus 14, and, for example, sends a vertical synchronization request signal VSR after printing preparation is completed.
EQI is outputted to the vertical synchronization input port VSREQ of the controller 15 via the buffer element 1. E0 to E are print enable signals, which are output from the control circuit 13 to the driver circuit 10.

FIG. 2 is a timing chart illustrating the sending timing of each signal shown in FIG. 1, and the same components as in FIG. 1 are given the same reference numerals.

Next, the operation shown in FIG. 1 will be explained with reference to FIGS. 3 and 4.

FIG. 3 is a flowchart illustrating an example of a binary image data creation processing procedure according to the present invention.

Note that (1) to (13) indicate each step.

First, during printing processing, the interface circuit 12 is connected from the controller 15 side via the parallel interface bus 14.
The command is taken in (1).

The command taken into the interface circuit 12 is read by the control circuit 13 (2) The command is analyzed (3) Then, as a result of the analysis, it is determined whether it is a print start command or not (4) If no, Execute other command processing, and if YES (print start command), control circuit 1
3 prepares for printing processing and sends a vertical synchronization request signal VSREQI, which is an image data request signal, to the controller side via the buffer element 1 (5). In response to this, the horizontal synchronization signal BD is sent from the controller 15 side.
S is sent out through the buffer element 1 (6), and this horizontal synchronizing signal BDS is sent to the video counter circuit 6. Line counter circuit 7. The signal is input to the control circuit 13.

Next, the video counter circuit 6 receives the horizontal synchronizing signal BD.
In preparation for counting the serial image data sent out immediately after the S input, the line counter circuit 7 starts counting the number of lines of the image (7).

Further, in parallel with this, an interrupt is generated in the control circuit 13, but the first time, no processing is executed and the processing ends.

Then, the superimposed image signal MVO, which is sent out immediately after the next horizontal synchronization signal BDS, is waited for to arrive at the phase detection circuit 2 and the timing extraction circuit 4 via the buffer element 1 (8), and the superimposed image signal MvO is When the signal arrives, the phase detection circuit 2 determines whether there is a clock component in the first half of one image data cycle representing a black image, or whether there is a clock component in the second half of one image data cycle representing a white image9). The image data creation circuit 3 is notified (10). Furthermore, the timing extraction circuit 4 extracts a clock component from the sent superimposed image signal MVO (11), and the timing generation circuit 5 generates a synchronization clock for the binary image data VIDEO from this component.
An instruction is given to (12).

Next, the image data creation circuit 3 creates binary image data VIDEO based on the determination result from the phase detection circuit 2, and outputs it to the AND gate 8 (13).

FIG. 4 is a flowchart illustrating an example of a synchronization timing signal generation processing procedure according to the present invention. In addition, (1
) to (4) indicate each step.

The phase detection circuit 2 determines the phase of the superimposed image signal MVO input from the controller 15 (1).

Next, the timing generation circuit 5 generates a synchronous timing signal VCLK that becomes a synchronous clock for the binary image data VIDEO based on the instruction from the timing extraction circuit 4 (2), and transmits the generated synchronous timing signal VCLK to the shift register circuit 11 and the synchronous timing signal VCLK. The signal is sent to the video counter circuit 6 (3).

The video counter circuit 6 then counts the serial image data based on the synchronization timing signal VCLK (4).

At this time, the output of the line counter circuit 7 is maintained in the "off" state until the lines for one page are counted, and is turned "on" at the end of counting.

Therefore, the binary image data V from the image data creation circuit 3
IDEO is taken into the shift register circuit 11 based on the synchronous timing signal VCLK created via the AND gate 8.

Following the same procedure, one line of image data (binary image data VI DEO) is transferred to the shift register circuit 1.
1, the video counter circuit 6 sends a transfer pulse for the image data in the shift register circuit 11 to the driver circuit 10 to the shift register circuit 11.

The shift register circuit 11 starts transferring one line of image data to the driver circuit 10 in response to this transfer pulse. As a result, the drive of the thermal head 9 for the serial two-value image data of the first line enters the standby state.

Next, as the second line processing, the horizontal synchronizing signal BDS is sent from the controller 15 side to the video counter circuit 6 through the buffer element 1. The signals arrive at the line counter circuit 7 and the control circuit 13, respectively.

Then, in the control circuit 13, when the printing is in the standby state, a print enable signal E is sent to the lid driver circuit 10 for printing processing. -E3 is output in a time-division manner with a time width that matches the print density. Print processing is performed based on this output.

Immediately after the second horizontal synchronization signal BDS, the second line of serial binary image data is taken into the shift register circuit 11 via the same route as the first line.

Thereafter, the above process is similarly repeated for the number of lines for one page.

When the line counter circuit 7 counts up to (the last line +1), the output signal of the line counter circuit 7 is turned on, the ant gate 8 is turned off, and the binary image data VIDEO is transferred to the shift register circuit 11. Input is stopped.

Thereafter, a transfer pulse from the video counter circuit 6 is sent to the shift register circuit 11, and after one line of serial binary image data is transferred to the driver circuit 5810, a print enable signal E is sent from the control circuit 13. ~E3 is output and the printing process is completed.

In the above embodiment, the present invention is applied to a thermal printer as the printer device, but the present invention can be easily applied to other serial printer devices.

(Effects of the Invention) As explained above, the present invention includes a superimposing means for creating a superimposed image signal by superimposing timing information for determining synchronization timing with a printing section on a video signal, and an image signal created by the superimposing means. a phase detection means for detecting the phase of a video signal from a superimposed image signal; an image data creation means for creating image data to be transferred to a printing section based on the phase of the video signal detected by the phase detection means; Since the timing signal creation means extracts timing information from the image signal and creates a synchronized timing signal for processing the image data created by the image data creation means, the circuit configuration can be easily changed without significantly changing the circuit configuration. It becomes possible to accurately determine the synchronization timing of the transferred serial image data without arranging a dedicated clock signal line for transferring the serial image data to the printer device. Therefore, the excellent effect of being able to perform high-quality printing processing is achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the configuration of a printer device showing an embodiment of the present invention, FIG. 2 is a timing chart explaining the sending timing of each signal shown in FIG. 1, and FIG. FIG. 4 is a flowchart illustrating an example of a binary image data generation processing procedure according to the present invention. In the figure, 1 is a buffer element, 2 is a phase detection circuit, 3 is an image data creation circuit, 4 is a timing extraction circuit, 5 is a timing creation circuit, 6 is a video counter circuit, 7 is a line counter circuit, 8 is an AND gate, 9 is a thermal head,
10 is a driver circuit, 11 is a shift register circuit, 12
13 is an interface circuit, 13 is a control circuit, 14 is a parallel interface bus, 15 is a controller, and 16 is an image information processing section. Diagram: Funeral map

Claims (1)

[Claims] In a printer device having a printing section that performs printing processing based on a video signal input from a host via an asynchronous video interface, timing information for determining synchronization timing with the printing section is superimposed on the video signal. a superimposing means for creating a superimposed image signal, a phase detecting means for detecting the phase of the video signal from the superimposed image signal created by the superimposing means, and a phase of the video signal detected by the phase detecting means. an image data creation means for creating image data to be transferred to the printing section based on the above, and a synchronized timing for extracting the timing information from the superimposed image signal and processing the image data created by the image data creation means. 1. A printer apparatus comprising: timing signal generating means for generating a signal.