JPH0263314B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a two-dimensional solid-state image sensor having a feature in signal readout.

In general, a solid-state image sensor is a device that has a photodetector and a scanning mechanism mounted on a semiconductor material such as silicon, and if an appropriate photodetector is selected, it is possible to capture images from the visible to the infrared region. It is what it is. Compared to conventional image pickup tubes, solid-state image sensors have the advantage of being smaller, lighter, and more reliable, and require very few adjustments when manufacturing an image pickup device, and are attracting attention from a wide range of fields. are collecting.

Now, the conventional scanning mechanism for solid-state image sensors is
Those using MOS switches and CCD (Charge)
Coupled Device)
In the case of the former, which uses MOS switches, spike noise caused by the MOS switch used when reading the signal mixes into the signal, lowering the S/N, and this spike noise differs between the columns being read. This becomes noise called fixed pattern noise, which has the disadvantage of further lowering the S/N ratio, and therefore cannot be used for weak signal detection that requires a high S/N ratio. In addition, in the latter CCD method, especially the interline CCD method, which has been widely used recently because the photodetector can be freely selected like the former MOS method, there is a gap between the detector rows.
Since a CCD is arranged, it is desirable to design the area of the CCD section to be as small as possible in order to increase the effective area of the detector. On the other hand, the charge transfer ability of a CCD is proportional to the storage gate area per CCA stage, assuming the structure is the same. Therefore, reducing the area of the CCD section limits the maximum value of charge that can be handled. These problems are especially serious when detecting a small signal in a large background, such as with an infrared solid-state image sensor. Also,
CCDs are generally composed of two layers of polycrystalline silicon gate electrodes, and have the disadvantage that the process is more complicated than the one-layer gate electrode structure of the MOS method.

Therefore, the present invention has been made in view of the above-mentioned drawbacks, and it is a solid-state image sensor configured using a charge transfer element as a basic element. By transferring this region as one potential well, we can provide a solid-state imaging device with a large amount of charge that can be handled with less noise, and by using one high-resistance layer as the gate electrode of the charge transfer device, we have improved the structure and The purpose of this invention is to provide a solid-state image sensor that has a simplified process.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a solid-state imaging device according to the present invention, which is shown as a 3×4 array for simplicity.
In the figure, 1 is a photodetector arranged two-dimensionally on a semiconductor substrate, 2 is a transfer gate formed by a MOS transistor formed on the same substrate, and 3 is a vertical charge transfer element formed on the semiconductor substrate. ,
4 is an interface portion forming an interface with the horizontal CCD 5 formed on the semiconductor substrate, 6 is an output preamplifier, and 7 is the output of this preamplifier. In the solid-state image sensor configured in this way, the horizontal CCD 5 and output preamplifier 6 are
It may be exactly the same as a CCD type solid-state image sensor, and has features in the part related to vertical charge transfer, that is, the vertical charge transfer element 3 and the interface part 4.
This will be explained using FIGS. a to j and FIG. 3. First, the structure of this part will be explained using FIG. 2a. FIG. 2a shows a cross section taken along line A-A' in FIG. 1, and the vertical charge transfer element 3 has one high resistance layer, For example, a gate electrode 31 made of polycrystalline silicon doped with a small amount of As;
It is configured to have wirings 3-1 to 3-4 for applying a potential to. Further, the interface section 4 is composed of two gate electrodes 4-1 and 4-2, and the end of the interface section 4 is horizontal.
It is in contact with one gate electrode 5-1 of the CCD 5. And 8 is a semiconductor substrate,
A channel is formed under each gate. This channel may be a surface channel or a buried channel.

On the other hand, each gate electrode 31, 4-1, 4-2, 5
−1 is a clock signal φv ₁ as shown in FIG.
~φv ₄ , φ _S , and φ _T are applied, respectively. Note that the clock signals φv ₁ to _{φv 4} are applied to the wirings 3-1 to 3-4, respectively. Further, in this embodiment, an N channel is used, and in the case of a P channel, the polarity of the clock signal may be inverted.

Next, the vertical charge transfer shown in FIG. 2a will be explained based on FIGS. 2b to 2j. Figures 2b to 2j show the state of the channel potential corresponding to the position in Figure 2a at each timing, and Figure 2b shows the state of the channel potential corresponding to the position in Figure 2a at each timing.
This is the potential at the time corresponding to the timing _t1 in the figure. At this time, all of the clock signals φv ₁ to φv ₄ are at the “H” level, so a large potential well (hereinafter referred to as a potential well) is formed under the gate electrode 31, and the clock signals φ _S is at the "H" level higher than the clock signals φv ₁ to φv ₄ , so that the gate electrode 4-
A deeper potential well is formed below the gate electrode 4-2, and since the clock signal _φT is at the "L" level, a shallow potential well is formed below the gate electrode 4-2.
On the other hand, the horizontal CCD 5 is performing charge transfer in this state, and is reciprocating between potential states as shown by dotted lines in the figure. In this state, when any one transfer gate 2 in the vertical direction is turned on and the contents of the detector 1 are read out into the vertical charge transfer element 3, a signal charge Qsig is present at a predetermined position of the gate electrode 31. It is a matter of fact. Next, at the timing _t2 shown in FIG. 3, that is, when the clock signal _φv1 is set to the "L" level, as shown in FIG. 2c, the wiring 3-1
The lower potential well becomes shallower and wiring 3-1
A potential well having an inclination from the bottom to the bottom of the wiring 3-2 is formed. Therefore, the signal charge
Qsig is pushed in the direction of arrow A in FIG. 2 while expanding spatially. Furthermore, as shown in FIG. 3, the clock signals φv ₂ to _{φv 4} are sequentially brought to the _“ L” level at timings t ₃ , t ₄ , and t 5 , and
As shown in ~f, the potentials under the wirings 3-2 to 3-4 are sequentially brought to the "L" level, and
As shown in FIG. 3, the potential under the gate electrode 31 becomes shallower and the inclined portion moves in the direction of arrow A. As a result, the signal charge Qsig is pushed out in the direction of arrow A, and the clock signal _φv4 becomes "L". At the point when the signal charge Qsig is used up, the signal charge Qsig is stored in the potential well under the gate electrode 4-1. Note that, depending on the resistance value of the gate, for example, if the wiring 3-1 is "H" and the wiring 3-2 is "L", the current value flowing through the wirings 3-1 and 3-2 is determined, which determines the power consumption. Therefore, it is desirable to have a high resistance, but if the resistance is extremely high, the potential gradient between the wirings 3-1 and 3-2 will not be formed well when the wiring 3-2 is switched from "H" to "L". Therefore, the resistance value of the gate electrode 31 is
It is desirable to set it to 1MΩ/□~1GΩ/□. This value can be achieved, for example, by forming polycrystalline silicon by CVD and doping it with a small amount of arsenic. In addition, the gate electrode 4-1 has a signal charge Qsig
It needs to be large enough to store enough
As shown in the above embodiment, the clock signal φ _S is “H”
It is not necessary that the potential at the time is deeper than the potential below the wirings 3-1 to 3-4, and it may be the same depth. In this way, the signal charge Qsig
is collected on the gate electrode 4-1, and after the horizontal CCD 5 has finished scanning one horizontal line, the horizontal line in contact with the gate electrode 4-2 is collected at the timing _t6 shown in FIG.
The clock signal φ _H of the gate electrode 5-3 of the CCD 5 is set to "H" level, and the gate electrode 4-2
Since the clock signal _φT of is set to “H” level,
The potential under each gate is as shown in FIG. 2g. Note that, at this time, the potential under the gate electrode 4-2 is set to be higher than the potential under the gate electrodes 4-1 and 5-1, but it is not necessarily necessary to make the potentials higher, and the potentials may be at the same level. It's a good thing. Next, at timing _t7 shown in FIG. 3, the clock signal φ _S is set to "L" level, and as shown in FIG.
Since the potential below -1 becomes shallower, the signal charge
Qsig will be moved into the potential well below the gate electrode 5-1. Then the third
At timing _t8 shown in the figure, the clock signal _φT goes to "L" level, the potential under the gate electrode 4-2 becomes shallow as shown in FIG. 2i, and the signal charge Qsig is transferred by the horizontal CCD 5. It is something that becomes. That is, the signal (signal charge Qsig)
The horizontal CCD 5 that receives the signal sequentially transfers the signal to the output preamplifier 6. This is because when the signal is transferred to the horizontal CCD 5, the clock signals φv ₁ to φv ₄ and φ _S become “H” level again at the timing t ₉ shown in FIG. 3, and the same conditions as at the timing t ₁ are established. , and the cycle described above will be repeated.

In the explanation of the operation of the above embodiment, the case where the contents of the detector 1 in one vertical charge transfer element 3 is read out is explained, but each vertical signal transfer element 3 simultaneously performs the same operation as described above. This is what is being done.

By doing this, the charge transfer is
Like the CCD method, it is carried out through the potential well, so there is no spike noise like in the MOS method.Moreover, the amount of signal charge that can be handled is determined by the potential well of the entire vertical line segment of the vertical charge transfer element 3, so it is extremely In addition, it can be made large enough even if the width of the channel forming the vertical signal line is made small.
In addition, the gate electrode 4-1 and the horizontal CCD 5 can be formed outside the detector 1 array, and there are fewer restrictions on size, so it is easy to increase the size of the interface section 4 or the horizontal CCD 5 according to the required amount of charge. It is what it is. Further, in the above embodiment, the vertical charge transfer element 3 is scanned during one horizontal period (normally, the longest one is transferred through the vertical charge transfer element 3 over a period of nearly one frame time). Since the time that the charge Qsig exists in the channel is shortened, it also has the effect of reducing channel leakage current and smear.

In addition, in the above embodiment, a case was described in which the clocks were composed of four clocks φv ₁ to φv ₄ given to the vertical charge transfer element 3, but there is no limit to the number of clocks as long as there is a plurality of clocks, and transfer efficiency may be taken into consideration. The number of clocks can be determined by Furthermore, although the channel of the vertical charge transfer element 3 has been described as being of N type, it may also be of P type. Furthermore, in the above embodiment, the gate electrode constituting the vertical charge transfer element 3 and the gate electrode constituting the transfer gate 2 are separate gate electrodes, but a ternary clock signal as used in a conventional CCD is used. One gate electrode constituting the vertical charge transfer element 3 and the transfer gate may be used as a common gate electrode. Further, the timing of the clock necessary for scanning is not limited to this example, and it is sufficient that the potential barrier moves in the direction of signal propagation.

As described above, according to the present invention, in a solid-state image sensor having a scanning mechanism for reading and outputting the output from a photodetector, the gate electrode of the vertical charge transfer element is connected to a high resistance element and a clock signal is applied to the high resistance element at multiple locations. This configuration not only simplifies the process and structure, but also provides the extremely excellent effects of reducing noise and increasing the amount of signal charge that can be handled.

[Brief explanation of the drawing]

1 to 3 show an embodiment of the solid-state imaging device according to the present invention, FIG. 1 is a block diagram of the solid-state imaging device, FIG. 2a is a cross-sectional view taken along line A-A' in FIG.
2b to 2j are potential diagrams for explaining the operation in section a of FIG. 2, and FIG. 3 is a clock timing diagram. Note that the same reference numerals in each figure indicate the same or corresponding parts. 1...Photodetection section, 2...Transfer gate,
3... Vertical charge transfer element, 31... Gate electrode,
3-1, 3-2, 3-3, 3-4...Wiring, 4...
...Interface section, 4-1, 4-2...gate electrode, 5...horizontal CCD, 5-1...gate electrode, 6...preamplifier, 8...semiconductor substrate.

Claims (1)

[Claims] 1. In a solid-state imaging device comprising a plurality of photodetectors, a vertical charge transfer device, and a horizontal charge transfer device,
The vertical charge transfer element is connected to a MOS gate electrode from an insulating film formed on a semiconductor substrate and a resistive conductor layer formed on the insulating film, and to the MOS gate electrode at at least two places, and the MOS gate electrode What is claimed is: 1. A solid-state imaging device comprising: a wiring for applying a potential to the wiring; and performing vertical charge transfer by sequentially changing the potential of the wiring. 2 The scanning circuit that changes the potential of the wiring is a photodetector,
2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is formed on the same semiconductor substrate on which the vertical charge transfer device and the horizontal charge transfer device are formed.