JPH0263314A - Spread spectrum wave generator - Google Patents

Abstract

PURPOSE:To obtain an accurate and stable spread spectrum wave without any frequency deviation by constituting the circuit with the combination of the 1st counter for setting frequency division data, a logic circuit for end of output, the 2nd counter for frequency division count and a frequency divider. CONSTITUTION:The 2nd counter 12 increments a data from the 1st counter according to a clock from a clock generating source 14 and outputs a carry signal to a frequency divider 15 and the 1st counter 11. The processing is repeated and a digital chirp wave is outputted from the frequency divider 15. When a data outputted from the 1st counter 11 reaches a prescribed setting value, the logic circuit 13 stops the clock to the 2nd counter 12 to stop the production of the chirp wave. Since the frequency divider 15 frequency-divides the clock accurately, an accurate and stable chirp wave is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a spread spectrum wave generator used for data communication between a continuous writing device and a non-contact memory module, for example.

[Prior Art] A conventional generator for generating a spread spectrum wave, such as a chirp wave, is shown in FIG. 4.

In FIG. 4, 1 is a voltage controlled oscillator (hereinafter referred to as VCO>
For example, if you want to create a chirp wave, use this V
By inputting a triangular wave 2, which is a control signal, to CO1, a chirp wave 3 or 4 was generated. Also, if you want to create a spread spectrum wave other than a chirp wave, you can create the desired spread spectrum wave by inputting the corresponding voltage value.

[Problems to be Solved by the Invention] However, in such conventional spread spectrum wave generators, vCO generally has poor stability, the frequency fluctuates depending on temperature and power supply voltage, and the input voltage and output frequency vary. The problem is that it is extremely difficult to create accurate and stable chirp waves because the relationship between the two is non-linear.

In addition, since a VCO generally oscillates at a steady state at a frequency called a free-running frequency, when generating a pulse-like chirp wave, a gate circuit such as an analog switch is required at the output section of the VCO, and The gate must be opened and closed at the timing of the oscillator output zero cross.
Another problem was that it required an extremely complex control circuit.

The present invention has been made in view of such conventional problems, and provides a spread spectrum wave generator that can output an accurate and stable desired spread spectrum wave and has a simple circuit configuration. It is intended to.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a first counter that outputs data counted up or down by inputting a carry or carry down signal, and an output termination logic circuit to which data and a clock from a clock generation source are input; a second counter that increments the data according to the clock from the logic circuit and outputs the carry or carry-down signal; A frequency divider that divides the frequency of the carry or carry-down signal to be output.

[Function] In the present invention, a first counter for frequency division data setting, a logic circuit for output termination, a second counter for frequency division 1 direct count,
Since the circuit is configured by combining a frequency divider and a frequency divider, it is possible to obtain an accurate and stable spread spectrum wave with no frequency deviation.

Further, by using predetermined setting data of the first counter, input of the clock to the second counter can be stopped, generation of the spread spectrum wave can be stopped, and the output of the spread spectrum wave can be set to only the set waveform. Furthermore, vCO
This eliminates the need for circuits such as voltage source circuits that are input to the circuit, reduces the number of parts, simplifies the circuit configuration, and saves power consumption.

U example] Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention.

First, to explain the configuration, in FIG. 1, 11 is a first counter for setting frequency division data, and after the first counter 11 is cleared by a start signal, the carry from the second counter 12 for counting frequency division value is Data counted up or down by inputting a signal @ (carry) or a borrow signal @ (carry down) is output to the logic circuit 13 and the second counter 12.

Depending on whether the first counter 11 counts up or down, it is determined whether the frequency of the output chirp wave gradually increases or decreases. Furthermore, when the data output by the first counter 11 reaches a certain set value, the logic circuit 13
Accordingly, the clock input to the second counter 12 is stopped, and the generation of the chirp wave is stopped.

14 is a clock generation source, and the clock generation source 14 generates a clock and sends it to the logic circuit 13.

Data is input from the first counter 11 to the logic circuit 13, and the logic circuit 13 supplies a clock to the second counter 12, but as mentioned above, when the data reaches a certain set value, it stops outputting the clock. do.

The second counter 12 counters the first counter 11 according to the clock.
, and outputs a carry signal to the frequency divider 15 and the first counter 11, respectively. The frequency divider 15 divides the frequency of the carry signal from the second counter 12 and outputs a digital chirp wave.

Next, the operation will be explained.

The first counter 11 is cleared by the start signal, and the count-up or count-down data is sent to the logic circuit 13 by the carry signal from the second counter 12.
and output to the second counter 12.

The second counter 12 increments the data from the first counter 11 according to the clock from the clock generation source 14 inputted via the logic circuit 13, and outputs a carry signal to the frequency divider 15 and the first counter 11. .

These steps are repeated, and the frequency divider 15 outputs a digital chirp wave.

Here, when the data output by the first counter 11 reaches a certain set value, the logic circuit 13 stops the clock to the second counter 12 and stops generating the chirp wave.

FIGS. 2(a) and 2(b) respectively show the output chirp waves, in which (a) shows the waveform when the first counter 11 counts up, and (b) in the figure shows the waveform when the first counter 11 counts up.
Shows the waveform when counting down. That is, when the first counter 11 counts up, the frequency of the chirp wave gradually increases, and when the first counter 11 counts down, the frequency of the chirp wave gradually decreases.

In this way, since the frequency divider 15 accurately divides the frequency of the lock, it is possible to generate an accurate and stable chirp wave without frequency deviation. In addition, only a desired chirp wave can be output by an external start signal and a stop signal based on an internal setting value. Further, the start signal can be started not only by clearing, but also by setting predetermined data and loading the data. Therefore, you can start from any frequency. In general, since a circuit such as a voltage source circuit input to CO is not required, the number of parts is reduced, the circuit configuration can be simplified, and power consumption can be reduced.

Next, FIG. 3 is a diagram showing another embodiment of the present invention.

In this embodiment, there is an RO between the first counter and the second counter.
This is an example in which M is provided.

In FIG. 3, 16 is a ROM, and this ROM 16
is provided between the first counter 11 and the second counter 12. The first counter 11 here is for generating a ROM address, and the data output from the first counter 11 becomes the address of the ROM 16. In the ROM 16, data including a stop signal, which creates a spread spectrum wave such as a chirp wave or other PN series, is written. The ROM 16 outputs data corresponding to the address to the logic circuit 13 and the second counter 12.

The second counter 12 increments the data output from the ROM 16 via the logic circuit 13 according to the clock from the clock source 14, and outputs a carry signal to the frequency divider 15 and the first counter 11.

The carry signal inverts the output of the frequency divider 15 and increments the first counter 11. These steps are repeated to output a spread spectrum wave.

Then, the clock to the second counter 12 is stopped by a stop signal from within the ROM 16, and the generation of the spread spectrum wave is stopped.

In this embodiment, a spread spectrum wave such as a chirp wave or other PN series can be created using the data written in the ROM 16, and only a desired spread spectrum wave can be output.

[Effects of the Invention] As described above, according to the present invention, accurate and stable spread spectrum waves without frequency shift can be generated. Further, by using an external start signal and a stop signal based on an internal setting value, it is possible to output the spread spectrum wave only in the set waveform. Roughly,
Since a circuit such as a power supply circuit input to the vCO is not required, the number of parts is reduced, the circuit configuration can be simplified, and power consumption can be saved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 (
FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. 4 is a diagram showing a conventional example. In the figure, 11... First counter, 12... Second counter, 13... Logic circuit, 14... Clock generation source, 15... Frequency divider, 16... ROM0

Claims (2)

[Claims] (1) a first counter that outputs data counted up or down in response to input of a carry or down signal, and an output termination logic circuit that receives data from the first counter and a clock from a clock generation source; a second counter that increments the data according to a clock from a logic circuit and outputs the carry or carry down signal; and a frequency divider that divides the frequency of the carry or carry down signal output from the second counter. A spread spectrum wave generator characterized by: (2) Data from the first counter is input as an address between the first counter and the second counter, and the written data corresponding to the address is output.
2. The spread spectrum wave generator according to claim 1, further comprising an OM.