JPH0262975B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field to which the invention pertains) The present invention relates to echoes caused by impedance mismatching of two-wire/four-wire conversion circuits in long-distance telephone lines, or wrap-around echoes between speakers and microphones that occur in remote telephone conferences, etc. It concerns an echo canceller that cancels the .

(Prior Art) A conventional device of this type will be explained using figures.

FIG. 1 is a block diagram showing an example of the configuration of a conventional echo canceller. 1 is a received signal input terminal, 2 is a received signal output terminal, 3 is a transmitted signal input terminal, 4 is a transmitted signal output terminal, and 5 is an echo path. , 6 is a subtractor,
7 is a convolution integrator, 8 is an X register that stores the received input signal and provides input data for the convolution integrator 7, and 9 is an H register that stores estimated parameters of the impulse response of the echo path, as well as a new correction amount for each sample. 10 is a ΔH generation circuit that calculates the correction amount, and 11 is a square sum circuit that calculates the sum of squares of the contents of the X register. , 12 is an input terminal for setting the loop gain α, and 13 is a transmission line.

The ΔH generation circuit 10 multiplies the output of the subtracter 6, that is, the error output signal, and the loop gain α, and multiplies the result of dividing by the output signal of the sum of squares circuit 11 by the output of the X register 8, and performs the correction described above. This is a block that calculates the amount. This configuration is well-known as an echo canceller using the standard learning identification method, and its operation is described in detail in "Applications of Digital Signal Processing" edited by the Institute of Electronics and Communication Engineers, pages 216-221, and will be explained here. is omitted. Also, there is a configuration similar to this that excludes the square sum circuit 11, but basically the operation is the same as the echo canceller based on the standard learning identification method and is included in this, so below we will discuss the standard learning identification method. The case using the identification method will be explained. In addition, in Fig. 1, the echo path side and the transmission path side are equipped with an A/D and an A/D as appropriate depending on the type of signal.
It is assumed that a D/A converter is inserted and digital processing is performed as the operation of the echo canceller.

Now, in the standard learning identification method, the sequential modification formula for the estimated impulse response vector Hj, which represents the contents of the H register as an N-dimensional vector, is given by the following formula.

Hj+1=Hj+αXj ej／ _N-1 〓 ^k=0 (Xj−k) ² …(1) Here, Xj is the input signal vector at time t=jT (T=sample interval), and ej is the subtractor output, that is, the error output It's a signal.

In this conventional echo canceller configuration, the loop gain α is given as a fixed constant, so this will be referred to as a fixed loop gain method. Furthermore, in order for the echo canceller to guarantee stable adaptive operation, it is necessary that 0<α<2 for α. Furthermore, considering the amount of echo cancellation and the convergence time, the condition for the loop gain α is 0<α≦1 (2).

According to the configuration based on this standard learning identification method, the amount of echo cancellation and the convergence time are in a trade-off relationship with respect to a constant loop gain α. That is, in order to increase the amount of echo cancellation, α must be chosen smaller, and in order to shorten the convergence time, α must be set to a larger value.

FIG. 2 is a diagram for explaining the convergence characteristics of a conventional echo canceller, and shows the above relationship, with ERLE (echo return loss improvement amount) plotted on the vertical axis and time t plotted on the horizontal axis.

Therefore, the conventional device of this type has the disadvantage that it is not possible to simultaneously improve the echo cancellation amount and the convergence time for a constant α.

(Object of the Invention) In order to eliminate the above-mentioned drawbacks, the present invention shortens the convergence speed and secures the required amount of echo cancellation by making the modified loop gain α variable. Explain.

(Structure and operation of the invention) FIG. 3 is a block diagram of an embodiment showing the structure of the invention, and 1 to 13 in the figure are the same as in FIG. 1. 20 is a loop gain control circuit which inputs the error signal ej, and outputs the error signal series ej, ej-1, ..., ej-r, of the current and past samples.
...(r; positive integer) and has an averaging function and an echo canceler function to output a loop gain that ensures stable adaptive operation.

FIG. 4 shows a first embodiment showing the details of the loop gain control circuit 20 of FIG.
is the signal input terminal to which the error signal ej is input. 22
23 is a square circuit, and 23 is a linear filter, such as a moving average filter or a recursively configured integrator. 24 is a signal output terminal.

The configuration of the echo canceller of the present invention is similar to the conventional case where α is fixed, except that the loop gain changes from α to αj and changes over time depending on the history of the error signal ej.

As configured as described above, if the echo canceller of the present invention starts convergence operation for input signal Xj from time j = 0, immediately after the start of convergence, the pulse transfer function of echo path 5 Difference in pulse transfer function of H register 9 in cellar (specifically, absolute value of difference in impulse response vector)
is large, the error signal ej also becomes large. Therefore, at this time, the correction amount, which is the output of the correction amount ΔH generation circuit 10, also increases because the output of the sum of squares circuit 11 increases in accordance with the amplitude of ej. On the other hand, since the amount of correction is increased, the difference in pulse transfer functions decreases rapidly over time compared to the fixed loop gain method, and the error signal ej also decreases more quickly. Therefore, the amount of correction becomes smaller accordingly, so the amount of improvement in echo return loss (ERLE) is the same as when α is small.
converges to ERLE.

FIG. 5 shows a second embodiment showing the details of the loop gain control circuit 20 of FIG.
23 are the same as in FIG. 25 is a first clipping circuit for clipping the output of the linear filter to a value within the range of αj in which the echo canceller should operate stably, that is, 0≦αj≦α _nax ≦1; 26 is a signal output terminal; Also, the first clip circuit 25 of FIG. 5 can be replaced by a second clip circuit having a lower limit value and an upper limit value. At this time, αj satisfies 0≦α _nio ≦αj≦α _nax ≦1. In this way, it is possible to prevent the adaptive operation from stopping or the transient characteristics from deteriorating due to αj becoming 0 or too small, and it is also possible to increase the degree of freedom in designing the filter in the loop gain control circuit.

FIG. 6 is a third embodiment showing details of the block of the loop gain control circuit 20 in FIG.
23 are the same as in FIG. 27 is a circuit (a power of 2 quantizer) which outputs a positive number and a value of a power of 2 less than 2 (2 ^-n ; n is a non-negative integer), which is the clip circuit shown in FIG. is a signal output terminal. Here, the power-of-2 quantizer 27 has a function of outputting a signal obtained by performing quantization operations such as rounding on the next lower bit of the first appearing 1 for an input of 1 or less expressed in binary. This is a circuit with Therefore, the output of the power of 2 quantizer 27 becomes a value of the power of 2. When this is used, the ΔH generation circuit has the advantage that a multiplier is not actually required to multiply the loop gain, and only a scaling operation is required.

Furthermore, the squaring circuit 22 in FIGS. 4 to 6 can be replaced with an absolute value circuit that outputs the absolute value of the input signal. In this case, since there is no square circuit, there is an advantage that the circuit configuration is simple.

In addition, when realizing an echo canceller, the circuit configuration differs depending on the signal format inside the circuit, such as fixed point, floating point, calculation format, etc.
The present invention can improve the convergence characteristics of the conventional fixed loop gain method without relying on these.

FIG. 7 is a diagram illustrating a comparative example of the convergence characteristics of the echo canceller of the present invention and the convergence characteristics of a conventional echo canceller confirmed by computer simulation. The configuration of the loop gain control circuit 20 consists of an absolute value circuit, a linear filter that performs uniform averaging, and a second clip circuit connected in cascade. In this example, the number of taps N of the adaptive filter that performs convolution integration, the loop gain generation formula, and the upper and lower limits of the clip circuit are respectively N=1000 αj=K(|ej|+|ej−1|) α _nax =1 , α _nio = 0.25. As can be seen from this, compared to the conventional fixed loop gain method A, the echo canceller of the present invention has almost the same characteristics as the fixed loop gain method when α = 1 at the initial convergence as shown in B, and in the steady state shows the echo cancellation characteristics of the fixed loop gain method with α=0.25.

(Effects) As explained above, according to the configuration of the present invention, by simply adding a few circuits to the conventional echo canceller circuit, convergence operation that significantly improves ERLE can be performed within a short period of time, and steady-state operation can be performed. Since a sufficient ERLE can be obtained in the state, the conventional fixed loop gain method has the advantage of fast convergence speed when α = 1, and the advantage of having a large ERLE when α is small. There is an advantage of having both.

In addition, with an echo canceller, when both parties talk at the same time (double talk), the echo path estimation operation is disturbed by noise from the near-end talker, and double talk detection control is required to prevent this.
According to the configuration of the present invention, since the convergence operation time is shortened, the probability of ERLE deterioration due to the occurrence of double talk is reduced, and the design of the order of the filter of the loop gain control circuit, etc. There is an advantage that the degree of deterioration of ERLE can be suppressed to a small level.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration example of a conventional echo canceller, FIG. 2 is a diagram showing convergence characteristics of a conventional echo canceller, and FIG. 3 is a block diagram of an embodiment showing the configuration of the present invention. 4, 5, and 6 are diagrams showing the first, second, and third embodiments showing the details of the loop gain control circuit in FIG. 3, respectively, and FIG. FIG. 3 is a diagram for comparing and explaining convergence characteristics of cancellers. 1...Reception signal input terminal, 2...Reception signal output terminal, 3...Transmission signal input terminal, 4...Transmission signal output terminal, 5...Echo path, 6...Subtractor, 7
...Convolution integrator, 8...X register, 9...
H register and H register update circuit, 10...
ΔH generation circuit, 11...Square sum circuit, 12...Loop gain setting terminal, 13...Transmission line, 20...
Loop gain control circuit, 21...signal input terminal,
22... Square circuit, 23... Linear filter, 2
4, 26, 28...Signal output terminal, 25...Clip circuit, 27...2 power quantizer.

Claims (1)

[Claims] 1 N samples of received input signal (N: positive integer)
An a subtracter that subtracts the convolution output signal, which is a pseudo echo signal, from a transmission input signal containing The adder is connected to be stored, and the subtracter output signal, which is an error signal, is input, and the weighted average value or integral value is output (averaged) for the error signal series of the current and past samples. nonlinear filter (loop gain control circuit) with non-negative output signal
and the error signal is a first input signal, the output signal of the X register is a second input signal, and the output signal of the loop gain control circuit is a third input signal, and these first, second, and third input signals are An echo canceller comprising a correction amount generation circuit that sequentially generates and outputs a product of input signals as a correction amount of the estimated parameter. 2. The echo canceller according to claim 1, characterized in that the nonlinear filter (loop gain control circuit) is replaced with a cascaded configuration of an error signal square circuit and a linear filter having an averaging function. . 3. Replace the nonlinear filter (loop gain control circuit) with a cascade connection configuration of a square circuit, a linear filter with an averaging function, and a first clip circuit whose output upper limit value is 1 or less. An echo canceller according to claim 1, characterized in that: 4 The nonlinear filter (loop gain control circuit) is composed of a square circuit, a linear filter having an averaging function, and a second clip circuit whose lower and upper limits of the output of the linear filter are values of 0 or more and 1 or less. 2. The echo canceller according to claim 1, wherein the echo canceller is replaced with a cascade connection configuration. 5. The echo canceller according to claim 2, 3, or 4, wherein the square circuit is replaced with an absolute value circuit. 6 Set the first or second clip circuit to a positive number and a power of 2 less than or equal to 1 (2 ^-n ; n is a non-negative integer)
Claim 3 is characterized in that the circuit is replaced with a circuit (a power of 2 quantizer) that outputs
The echo canceller according to item 4, item 5, or item 5. 7. It has a square sum circuit that calculates the square sum of N samples of the contents of the X register, and a reciprocal circuit that calculates the reciprocal of the output signal of the square sum circuit, and the output signal of the reciprocal circuit is as described above. The correction amount generation circuit is connected to a fourth input signal terminal of a correction amount generation circuit, and the correction amount generation circuit receives the error signal, the output signal of the X register, the output signal of the loop gain control circuit, and the fourth input signal terminal.
Claims 1 and 2 have a function of outputting a product of four signals with an input signal of , and the output signal of the correction amount generation circuit is used as the correction amount of the estimated parameter. Section, Section 3, Section 4, Section 5
or the echo canceller according to item 6.