JPH0261889A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To equalize the operating margins of sense amplifiers by performing the same operation of the sense amplifier positioned at an outer peripheral part as that of the sense amplifier in a central part by arranging a dummy bit line with high resistance and connected to a power source at the outermost peripheral part of a bit line group. CONSTITUTION:Only a pair of bit lines are arranged at the outermost peripheral part of the bit line group, and the bit line is connected to the power source via the high resistance whose resistance value >=10kOMEGA. In such a way, it is possible to perform the operation of the sense amplifier being positioned at the outer periphery same as that of the sense amplifier in the central part, and to equalize the operating margins of sense amplifiers.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to a cell array arrangement of a dynamic memory.

[Conventional technology]

Semiconductor memory has a structure in which a large number of memory cells are arranged in a matrix, and any memory cell can be accessed by selecting word lines and bit lines that are orthogonal to each other. Therefore, a group of memory cells is arranged in a fixed repeating pattern. is made of. Here, attention will be paid to the sense amplifier operation for reading and amplifying memory cell information. In a dynamic memory, sense amplifiers connected to each bit line pair operate in one cycle. Furthermore, due to recent high integration, the distance between bit lines has become very short, and capacitive coupling between bit lines has become stronger. Therefore, during sensing operation, the influence of adjacent bit lines cannot be avoided. In the central part of the memory cell group, there are bit lines on both sides, and in this sense, all the sense amplifiers in the central part operate under the same conditions. However, with regard to the bit line pair and its sense amplifier located at the outermost periphery of the memory cell group, there are no bit lines on the outside anymore, and the conditions are not the same as those in the center.

In other words, the outermost bit line has no external bit line with capacitive coupling, resulting in an imbalance.

[Problem to be solved by the invention]

In the conventional configuration described above, the outermost bit line has no capacitive coupling with adjacent bit lines, resulting in unbalance.
This has the disadvantage of narrowing the operating margin of the sense amplifier.

[Means to solve the problem]

In the semiconductor memory of the present invention, a further pair of bit lines and a sense amplifier are arranged outside the outermost bit line pair.

〔Example〕

Next, the present invention will be explained using the drawings.

FIG. 1 shows an embodiment of the present invention. The cause of sense amplifier operation imbalance is the presence or absence of capacitive coupling with adjacent bit lines. In the embodiment shown in FIG. 1, attention is paid only to this point, and only one pair of bit lines is arranged at the outermost periphery of the bit line group, and this bit line is connected to the power supply through a high resistance. In a normal sense operation, one side of the l bit line connected to the sense amplifier is in an almost completely floating state, and the other is also grounded through the transistor of the sense amplifier, but its impedance is quite high. Therefore, it is appropriate for the resistance in the embodiment to have a value of several tens of ohms or more.

[Effects of the Invention] As explained above, the present invention arranges a dummy bit line or sense amplifier at the outermost periphery of a memory cell group, so that the operation of the sense amplifier located at the outer periphery is synchronized with that of the sense amplifier located at the center. This has the effect of making the operation margins equal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram illustrating the present invention in detail.

Claims (1)

[Claims] A semiconductor memory characterized by arranging dummy bit lines connected to a power supply with high resistance at the outermost periphery of a bit line group.