JPH0261771A - Logical circuit simulation system - Google Patents

Abstract

PURPOSE:To extract the pass of data, in which an attention signal is propagated, by investigating how the attention signal is transmitted in a logical circuit with a given test pattern. CONSTITUTION:Logical circuit information to be composed of the information of a component, which constitutes the logical circuit, the information of connecting relation for the component and the information of a logical circuit describing language, etc., the information of a circuit pattern for the logical circuit to execute simulation, the information of an input test pattern 2 of a change information for an input signal, which is inputted to the circuit pattern, and the information of attention signal indication 3 to give attention to the change of the respective signals in the circuit when circuit operation is simulated and to designate the attention signal are inputted to an event processing part 4 and the simulation processing of the test pattern is executed. A processed result is outputted as an attention signal trace list 5, which wholly records related events, and a simulation result 6 to output the time change of respective signal values in the circuit pattern.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention relates to a logic circuit simulation method (prior art) used to analyze the operation of a designed logic circuit. A logic simulator is used to analyze the operation of a designed logic circuit. A logic simulator receives a logic circuit description language, etc. as circuit information of the circuit to be simulated, and inputs an input test pattern and the contents of a memory as input signal change information, and simulates the circuit operation of the logic circuit. . One of these simulations is an event-driven simulation that efficiently simulates circuit operation by focusing only on changes in signal values within the circuit. is output as The designer examines the changes in each signal as a result of this output and examines whether one circuit is performing the desired operation.

In this way, when investigating the operation of a circuit, it is necessary to analyze the propagation of signal values based on changes in each signal as a result of simulation.

In addition, in event-driven logical simulation,
Since only the signal value that has changed is processed, even if the signal flow changes at a certain time in a certain part of the circuit and a different signal is transmitted, the signal value after the change will not be the same as the previous signal value. If the values are the same, no event will occur, and the propagation of the signal may not be understood just by looking at the propagation of the event.

(Issues to be solved by the invention!) In view of the above, the present invention aims to eliminate the drawbacks of the prior art described above, that is, to analyze the operation of a logic circuit using an event-driven logic circuit simulator. When extracting the influence of a signal on circuit operation as event propagation, if the value of a certain signal is affected by an event that occurred in the previous stage of that signal, but the signal value does not change, The purpose is to prevent the transmitted events from stopping there, and to separately retain only the events related to the signal of interest, making it easier to analyze the operation of the logic circuit.

Providing a flag area for identifying that event propagation is to be noted for a signal value of a certain component in circuit information including components constituting a logic circuit and connection relationships between each component, and using the circuit information. When performing logic circuit simulation using the event-driven method (selective trace method), events generated from signals of components whose flags are turned on are given different event types to distinguish them from other events. (Set the normal event as event type 1 and this event as event type 2) If you want to generate the next event from this different type of event (for example, let's say event type 2), change that event in the same way. The event type is 2. In the event processing section, if the value of the component signal is the same before and after processing the event transmitted from the previous stage,
If the component does not generate an event, but the event type is different, that is, the value before event processing is
previously determined by an event of event type 1,
If the event transmitted from the previous stage at the current time is event type 2, an event is generated for the component even if the value before processing and the value after processing of the event are the same.

(Example) Examples of the present invention will be described in detail below.

FIG. 1 is a system configuration diagram showing the logic circuit simulator method of the present invention. Information on the logic circuit to be simulated includes logic circuit information 1 consisting of information on the components constituting the logic circuit, information on connection relationships between the components, information on the logic circuit description language, etc., and information on the circuit pattern of the logic circuit to be simulated. When simulating the operation of one circuit, the change information of the input signal input to that circuit pattern is input to the information of test pattern 2, and when simulating the operation of one circuit, the attention is focused on the changes of each signal in one circuit, and the signal of interest is specified. The information of the signal instruction 3 and the event processing unit 4
is input, and the test pattern simulation process is performed. The processed results are output as a signal-of-interest trace list 5 that records all related events, and a simulation result 6 that outputs temporal changes in each signal value within the circuit pattern.

The operation of the system of the present invention will be explained using the circuit pattern shown in FIG. 2 as an example. The logic circuit targeted for this simulation has input terminals 301, 302, 303.3.
Signal C1 input from 04.305.306.307
, DI, D2. CLKI, C3, CLK2. C
2 is a D-type flip-flop 308.309.315.3
16. A signal 02°01 is outputted to output terminals 317 and 318 via a circuit element composed of selectors 310°311, 312.313 and an adder 314. FIG. 3 shows an example of an input test pattern when simulating this logic circuit. A simulation is performed based on the input test pattern shown in FIG. 3, and a trace list in the case where a predetermined signal at a predetermined time is specified as the signal of interest is shown in FIG. 4 and will be explained.

First, the signal CLKI input to the input terminal shown in FIG.
, CLK2. C1, C2, C3, Di<0 near)',
D2 (0 near) has changed to time 0 and is processed as an event. These change the value of each signal value table to 0
Change to

Regarding signal C1, the output of the inverter to which it is connected,
Generates an event that changes the signal CIN to the value 1. Similarly, signal C2 generates an event that changes signal C2N to the value 1, and the event of signal C2N causes the output of the selector to which it is connected, signal S4 (0: 7), to change to the value 1111.
An event is generated to change the value to 1111. In the event processing of signal C3 and signal 54 (0 near), the value of the adder output, signal S5<O near) is the initial value XXXxx
xxx remains, but the signal S5 < 0 near) is event type 2 because the trace instruction flag is ON.
event occurs. This event is signal 56 (0
signal 01 (0 near), signal 57 (0 near), signal 02<O near).

Next, at time 10, the signals C1, C2, and C3 change to the value 1, and each event is processed. Signal C3 and signal 54 (
0 near) event processing, adder output, signal 55
(0 near) remains at the initial value xxxxxxxxx, but signal 55 (0 near) indicates that the trace instruction flag is O.
Since it is N, an event of event type 2 occurs. Signal S6<0 near), S7<O near>, 01<
O Near>.

No event occurs at 02 (0 near).

Next, at time 20, the signal CLK 1 changes to the value 1, and event processing is performed. Then, signal 5L (0 near), S2<
O near>53 (0 near) becomes the value ooooooooo.

Then, an event of event type 2 occurs at signal 55 (0 near). This event is not propagated to its destination.

Next, at time 50, the signal CLK l changes to the value O, and the signal D
I (0 near) changes to the value 01010101, and the signal D
2 (0 near) changes to the value 11111111 and events are processed, but these events are not propagated to the connected destination.

Next, at time 70, the signal CLK2 changes to the value 1, and event processing is performed. Then, the signals S6<0 near>, 01<O
near) and signal 57 (0 near), 02 (0 near) to the value O
It is transmitted as an event of type 2.

Further, the trace instruction flag of the signal of interest can be turned on at any time. In the above example, at time 10
Assuming that the trace instruction flag of signal 55 (0 near) is turned ON at 0, in FIG.
By changing the value 1 to 20, the signal 51 (0 near)
An event occurs in which the value of signal S3<O near> changes to the value 01010101, the value of the signal 52 (0 near) changes to the value 1, 1111111, and the value of the signal S3<O near> changes to the value 11111111. The value of the adder output, signal S5<0 near>, is the value 11
111111, and an event occurs. Here, in the signal S5<0 near>, since the trace instruction flag is ON, an event of event type 2 occurs. This event propagates to signal 56 (0 near), signal 01 (0 near), signal 57 (0 near>, signal 02 (0 near>). However, their values are the values oooooooooo
It remains as it is.

At time 0, set the trace instruction flag of signal S5<0 near) to O.
An outline of the trace list when N is set is shown in Figure 4(a).
become that way. Further, the outline of the trace list when the trace instruction flag of the signal S5<O near> is turned ON at time 100 is as shown in FIG. 4(b).

From this trace list, it is possible to determine what path the signal of interest travels. Figure 4(a).

In the example of (b), the signal of interest 55 (0 near) is the signal 56 (
0 near).

01 (0 near) and signals S7<O near>, 02<O near). In this way, it is possible to obtain the path through which the signal of interest propagates based on the given input test pattern.

When generating a functional test that automatically determines a functional test pattern for transmitting a signal to a certain data path in a given logic circuit, a function test pattern that is activated (conveys a signal to a data path) with a basic test pattern given by the designer is used. When generating a functional test for a data bus that is similar to a data bus that is similar to a data bus, the data bus is determined from the basic test pattern given by the designer using the method described above, and a similar A data bus is applied to a functional test generator to determine an input test pattern that activates the similar data bus. In this way, it is possible to obtain an input test pattern that performs a similar function to the basic test pattern given by the designer.

The above-mentioned event processing will be explained in more detail in the following steps, and the operation flowcharts are shown in FIGS. 5 and 6. FIG. 5 shows an example of an event storage area, and FIG. 6 shows an example of part of a component table and a value table (signal value table).

The event storage area shown in FIG. 5 is made up of a time wheel (specifically, a list that goes around) 10 in which events are stored and a plurality of event lists 11 at the same time taken out from this time wheel 10. In each event list 11, individual events are connected by pointers. The relationship between these event lists is shown by an arrow 12 indicating a preceding event that causes the event to occur. The pointers in the event list 11 are an event list pointer 13, an event type 14, a previous event pointer 15, a pointer to the component table 16. Each list contains 17 value bit widths and 18 event values.

FIG. 6 shows component tables 19 and 20, value tables 21 and 22 of signal values in the circuit, and output destination connection table 23. The component table 19 includes an attribute 24, a trace instruction flag 25, a pointer 26 to the output Q value table, a pointer 27 to the output Q connection table, a pointer 28 to the input value table, and a pointer 29 to the input Q value table. ing. Value tables 21 and 22 show the event type identification flag 30 and its value 3.
It consists of 1.

Next, the processing steps of the event processing of the present invention will be explained. Incidentally, here, the term "event" refers to, when simulating circuit operation, focusing on changes in each signal and propagating the changes through the circuit as "events."

5tepl: Take out the event from the event storage area and update the value of the signal value table of the component corresponding to the event with the event.

Here, if the event type is type 2.

The identification name (or pointer to the identification name) of the component, event value, and time are registered in the trace list so as to maintain the context of the event. At this time, the event type identification flag in the signal value table is turned ON.

5 step 2: Extract the number of output connection destinations and connection destinations of the component.

step3: Repeat for the number of connection destinations.

5tep3.1: Calculate the output value for the input value of the component for each attribute (gate type) of the connected component.

5step 3.2: (υ The trace instruction flag of the component is ON, or the previous event (the event extracted with stepl) is event type 2, and the event type identification flag of the component is 0FF (the previous event is If the event type is 1), the event type of the event to be registered is set to 2, and the output value calculated in step 3.1 is stored as an event value in the event storage area.

■ If the previous event is event type 2 and the component's event type identification flag is ON (the previous event is event type 2), or the previous event is event type 1 and the component's event type identification If the flag is ON, 5 step 3
．． The output value calculated in step 1 is compared with the value in the signal value table, and if the values are different, the event type of the event to be registered is set to 2, and the output value is stored in the event storage area as an event value.

Compare the output value and the value in the signal value table, and if the values are the same, no event is generated.

(3) Component trace instruction flag is OFF
If F, the previous event is event type 1, and the component's event identification flag is OFF,
5. Compare the output value calculated in step 3.1 with the value in the signal value table, and if the values are different, set the event type of the event to be registered to 1, and store the output value as an event value in the event storage area. Compare the output value and the value in the signal value table, and if the values are the same, no event is generated.

〔Effect of the invention〕

According to the present invention, it is possible to extract the data path along which the signal of interest propagates without impairing the processing efficiency of the event-driven method, and without analyzing the time changes of each signal in the simulation results. In this way, we can understand how the signal propagates.

Furthermore, by using the functions of the present invention, data paths (paths along which the focused signal is transmitted) within a given logic circuit are activated according to a given basic human test pattern.
can be found. Find a similar data bus in a logic circuit from the data bus obtained from the basic human test pattern, pass the similar data bus to a functional test generation system, and generate a functional test for the similar data bus; It becomes possible to automatically generate an input test pattern that performs a similar functional operation to a given basic human test pattern.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of the system configuration showing the input and output of the simulator for detailed explanation of the present invention, Figure 2 is a circuit diagram of the logic circuit to be simulated, and Figure 3 is similar to Figure 2. Figure 4 is a signal diagram showing the input test pattern when simulating the logic circuit shown in Figure 4, which is a signal diagram showing the input test pattern shown in Figure 3 using the logic circuit shown in Figure 2. Part of trace list 1 to when signal 55 (0 near) is specified at time O and signal 5 at time 100 as the signal of interest.
FIG. 5 is a diagram showing a part of a trace list when 5 (0 near) is specified, and FIG. 5 is a diagram showing an event storage area. FIG. 6 is a diagram showing a component table, a value table, and a connection table. 1...Logic circuit information 2...Input test pattern 3--Attention signal instruction 4...Event processing unit 5...Attention signal related trace list 6...Simulation result agent Patent attorney Noriyuki Chika The same Mitsuyuki Matsuyama Figure 1 (J <) (J to m (J (J \ to (d> (b) Figure 1)

Claims (1)

[Claims] In an event-driven logic circuit simulator that analyzes the configuration and operation of a logic circuit based on circuit information such as a logic circuit description language, it has a means for specifying a signal of interest, and an event related to the signal of interest. It has a means to compare and set the value to distinguish it from other signals, a means to record all events related to the signal of interest, and a given input test pattern indicates that the signal of interest is logical. A logic circuit simulation method that allows you to investigate how information is transmitted within a circuit.