JPH034335A - Method and device for extracting route - Google Patents

Abstract

PURPOSE:To easily execute the trace of the flow of a signal inside a circuit even when the scale of a logic circuit is enlarged by using event information generated in simulating the logic circuit based on a network structure and a test pattern and the network structure. CONSTITUTION:From a logic circuit description prepared by a description preparing part 11, the network structure to be the information to express the connection information of a pin is extracted by a network structure extracting part 12, and a simulation is executed by a simulation executing part 13 based on the network structure and the test pattern to express an input series to the input pin of the circuit. When the simulation is executed, a route is extracted by a route extracting part 15 based on the event information and network structure. By an expected value comparing part 14, a simulation result and an expected value are compared, and thus, whether the circuit is operated as expected or not is decided. When the circuit is not operated as expected, the flow of the signal inside the circuit is traced based on the extracted route. The circuit description is corrected based on the trace result, and the above- mentioned processing is repeated again.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention is an object of the present invention, when verifying a logic circuit using a simulator, how an input signal moves inside the logic circuit using a given test pattern. The present invention relates to a route extraction method and a route extraction device for automatically extracting a route along which an input signal propagates based on event information in order to check whether the input signal has propagated to the destination.

(Prior Art) Conventionally, a simulator is often used as a means for verifying the design of a logic circuit before creating an integrated circuit chip. Logic circuit simulation is performed using information representing the connection relationship of pins in the circuit (network structure) and an input sequence to input pins of the circuit (test pattern). Whether or not the circuit is operating as expected as a result of the simulation can be determined by comparing the simulation results with expected values created based on specifications.

However, if the simulation results do not match the expected values, it is necessary to trace the signal flow inside the circuit in order to investigate the cause. Also, even if the simulation results match the expected values, in order to check whether the circuit is working correctly inside, it is still necessary to
It is necessary to trace the signal flow inside the circuit. Conventionally, in order to trace the flow of such a signal, a human being traces the signal propagation path while correlating simulation results with a circuit diagram or a circuit description.

When the scale of the logic circuit to be designed is relatively small, tracing can be done by humans tracing the signal propagation path while correlating the simulation results with the circuit diagram or circuit description, as has traditionally been done. seems possible.

However, as the scale of the logic circuit increases, the number of simulation results also increases accordingly, creating the problem that it becomes difficult to follow the simulation results manually.

(Problems to be Solved by the Invention) Conventionally, as the scale of logic circuits increases, it becomes difficult to trace the flow of signals in simulation.

The present invention has been made in consideration of the above circumstances, and its purpose is to make it possible to use a computer to search for the propagation paths of signals inside a circuit, so that even if the scale of the logic circuit becomes large, the circuit It is an object of the present invention to provide a route extraction method and a route extraction device that can easily trace internal signal flows and contribute to improving verification efficiency of logic circuits.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention employs the following structure and steps, and automatically performs route searching using a computer.

That is, the present invention provides a route extraction method for tracing a signal flow in logic circuit simulation, which includes:
The network structure of the circuit to be simulated is extracted from the logic circuit description written in the logic circuit design description language, and an event-driven logic circuit simulation is performed based on the network structure and the test pattern. This method uses a structure to extract routes activated by a test pattern.

The present invention also provides a route extraction device for carrying out the above method, including a network structure extracting unit for extracting a network structure of a circuit to be simulated from a logic circuit description written in a logic circuit design description language; An event-driven simulator that performs logic circuit simulation using the network structure and test pattern extracted by the structure extraction section as input, and outputs information on the events that have occurred, and the event information output from this simulator and the network structure extraction section. The present invention is further provided with a route extraction unit that extracts routes activated by the test pattern based on the extracted network structure.

(Operation) In the present invention, the register transfer level (
It is assumed that the circuit will be designed using the logic circuit design description language (RTL).

The network structure extraction unit extracts the connection relationships between bins in the logic circuit (data system, control system, clock system) from this logic circuit description.
A network structure representing the data system is extracted, and a correspondence relationship between the connection relationship (network structure) and the statement of the logic circuit description is attached to the connection relationship of the data system.

Next, a simulation is performed using an event-driven simulator using this network structure and test pattern, and event information is output. By providing a correspondence relationship with sentences in the network structure, event information can include pin event information and sentence event information.

Finally, based on this event information and the network structure, the route extractor searches for a route activated by the test pattern. In addition to pin events, event information includes statement event information, and the network structure has three types of connection relationships and correspondences between statements, so it becomes clear which statement in the logic circuit description was executed, and the correct route is taken. It becomes possible to search for

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a block diagram showing a schematic configuration of a route extraction device according to an embodiment of the present invention. Reference numeral 10 in the figure is an execution control unit that controls the operation of each unit, and this execution control unit 10 includes a description creation unit 11. Network structure extraction unit 12. A simulation execution section 13, an expected value comparison section 14, a route extraction section 15, etc. are connected.

The description creation unit 11 creates a logic circuit description using an RTL logic circuit design description language to be described later, and this logic circuit description is supplied to the network structure extraction unit 12. The network structure extraction section 12 extracts the network structure of the circuit to be simulated from the logic circuit description, and supplies this network structure to the path extraction section 15 together with the simulation execution section 13 .

The simulation execution unit 13 is an event-driven simulator, and the simulation execution unit 13 is an event-driven simulator.
, a logic circuit is simulated based on the network structure and test pattern. Simulation execution part 1
The simulation results in step 3 are supplied to the expected value comparison section 14, and the event information is supplied to the route extraction section 15. The expected value comparison unit 14 compares the simulation result with the expected value and determines whether the circuit is operating as expected. Furthermore, the route extraction unit 15 extracts routes activated by the test pattern based on the network structure and event information.

FIG. 2 is a flowchart for explaining a route extraction method using the above device and a subsequent logic circuit verification method. First, a network structure, which is information representing pin connection information, is extracted by the network structure extraction unit 12 from the logic circuit description created by the description creation unit 11, and this network structure and the input series to the input pins of the circuit are extracted. A simulation is executed by the simulation execution unit 13 based on the test pattern. When the simulation is executed, the route extraction unit 15 extracts a route based on the event information and network structure. A detailed explanation of this route extraction will be given later.

Further, the expected value comparison unit 14 compares the simulation result with the expected value, thereby determining whether the circuit is operating as expected.

If the circuit is not operating as expected, trace the signal flow inside the circuit based on the extracted route. Then, the circuit description is corrected based on the trace result, and the previous process is repeated again. If the circuit is operating as expected, it depends on whether or not to trace. If not, the process ends. When tracing, the signal flow inside the circuit is traced based on the extracted route. If the tracing result is normal, the process ends; if the trace is abnormal, the circuit description is corrected and the previous process is repeated again. In this way, route extraction and logic circuit verification are performed.

Next, the present invention will be explained in more detail with reference to specific examples.

The present invention requires an RTL logic circuit design description language. Furthermore, as a description method for the RTL language, a method is required in which the control system can be specified using a conditional statement, and the clock system can be specified using a clock specification. From the logic circuit description written in the RTL language having this feature, the connection relationships of pins in the logic circuit classified into control system, data transfer system, and clock system are extracted. - The connections between pins in the membrane are expressed as a single statement in the RTL description. Therefore, a connection relationship with a corresponding sentence is also established between the connections between pins.

FIG. 3 is an example of an RTL description, and FIG. 4 is a graph representing a network structure corresponding to the RTL description shown in FIG. In reality, this graph is represented on a computer using a specific data structure. It is represented by a round shape or a pin, and the arrow connecting the round shapes represents a connection relationship. ÷ represents a data system connection.

○±O corresponds to a sentence in RTL description. Each sentence in the description is given a unique sentence number, and O+O is given a corresponding sentence number. → represents a clock system connection or a control system connection. If the end of the → is a pin, it represents a clock system connection, and if the end of the → is a ÷, it represents a control system connection.

An event is a change in value. First, we will explain the event processing of the event-driven simulator,
Let's explain how to create event information. An event is a change in value. If there is no control system connection or clock system connection to the statement ■+■, if an event occurs at the pin ■, the statement ■+■ is evaluated, and if the value of the pin ■ changes, the event is propagated to the pin ■. do.

As a result, event information for pin ■, event information for sentence ■÷■, and event information for pin ■ are created. Also,
In order to understand the propagation route of the event, a connection relationship is established between the event information of the pin ■ and the sentence ■±■, and the event information of the sentence ■+■ and the pin ■.

When there is a control system connection (■→) in the sentence ■±■, there are the following two ways of propagation. First, when an event occurs on pin ■, check the value of pin ■, and if the value is appropriate, evaluate statement ■+■, and if the value of pin ■ changes, propagate the event to pin ■. let As a result, event information for pin ■, event information for sentence ■÷■, and event information for pin ■ are created. Also, pin■event information and sentences■÷
A connection relationship is established between the event information of ■, the event information of sentence ■±■, and the event information of pin ■.

Second, when an event occurs on pin ■, if the value of bin ■ is an appropriate value, evaluate sentence ■±■, and if there is a change in the value of pin ■, propagate the event to pin ■. As a result, pin ■ event information, sentence ■±■p event information,
Create event information for pin ■. Further, a connection relationship is created between the event information of pin ■ and the event information of sentence ■+■, and the event information of sentence ■÷■ and the event information of pin ■.

If the statement ■±■ has a clock system connection (■→), evaluate the statement ■+■ when the value of the pin ■ changes from 0 to 1,
If the value of pin ■ changes, an event is propagated to pin ■. As a result, pin ■ event information, sentence ■±■
Create event information for , and event information for pin■. In addition, event information for pin■ and event information for sentence■＋■,
A connection relationship is created between the event information of the sentence ■÷■ and the event information of the pin ■.

FIG. 5 is an example of a test pattern for verifying the circuit shown in FIG. 3. Below, a method for outputting simulation results (event information) when a simulation is performed using the network structure shown in FIG. 4 and the test pattern shown in FIG. 5 will be explained in order. Here, pin event information is represented by (bin name, value 1 time), and sentence event information is represented by (sentence number 1 time).

At time 0, Dl, C11, 'CI2. An event occurs on CLKI DI, 4B1010.0), (CIl, IBo, 0)
.

(CI2.IBI, 0) and (CLKI, IBo, 0) are created as event information. Also, due to the events (C11, lBO, o) and (CI2.IBI, 0), the sentence C0ND (0:1) Embroidery C11! ICI2 is evaluated and the event is propagated to C0ND. At this time, the event information is (COND<0:l) -Cl1jICI2 statement number,
Q) Create (COND<0:1>, 2BO1,0). Furthermore, pin C11 and statement C0ND(0:l) -Cl1jlC+
2゜pin C11 and sentence C0ND<0:1) -Cl1jl
A connection relationship is established between event information of C+2° statement C0ND<0:l)-C1111CI2 and pin C0ND<0:1).

There is a possibility that the event will be propagated to Tl due to the above event, but since the statement TI-ADD (R1, IBl, IBI) is evaluated and there is no change in value, the event will not be propagated to TI. This completes the event information at time 0. At time 50, an event occurs on CLKI. Therefore, event information (CLKI, lB1.50) is created. Here, since the value of CLKI has changed from 0 to 1, the sentence R1-Di R2-TI is evaluated. As a result, the event is propagated to R1, and (statement R1-Dl sentence number, 50) (R1 (0:3), 4B1010.50) is created. Also, a connection relationship is created between event information. Further, due to the event that occurred, the statement TI -ADD (R1, IBI, IBI) is executed,
Event propagates to TI. Therefore, (sentence Tl -AD
D (R1, IBl, 1BI) sentence number, 50) (TI,
4B1011.50) event information is created. Also, a connection relationship is created between event information. However, since the value of R2 does not change, l? No event occurs in 2. Now time 5
Processing of the event at 0 ends. At time 100, an event occurs in CLKI, but there is no event propagation due to this.

Therefore, the event information (CLKl, IBo, 100) is output and the processing of the event at time 100 ends. At time 150, an event occurs on CLKI. Here, since the value of CLKI has changed from 0 to 1, the sentence R1 Hatake old R2-TI is evaluated. Since there is no change in the old value, no event occurs in R1. However, since there is a value change in R2, an event occurs between 1 and 2. With this event,
Statement 01-R1 is evaluated and an event occurs at 01.

Since 01 is an output pin, event propagation ends here. Therefore, the event information created at time 150 is as follows.

(CLKI, IBl, 150) (Sentence R2-Tl sentence number, +50) (1?2 (0:3), 4 old and old 1.150) (Sentence 01-
R2 statement number, 150) (01 (0:3), 4131
011, 150) Furthermore, a connection relationship is created between event information.

FIG. 6 shows event information and connection relationships created when a simulation is performed using the network structure of FIG. 4 and the test pattern of FIG. 5. Below, a method for extracting routes activated by the test pattern shown in FIG. 5 will be described using the network structure shown in FIG. 4 and the event information shown in FIG. 6.

For example, the path through which data propagates to the output terminal is determined as follows. First, search for event information for pin 01. From this event information, the propagation of the event is traced in the reverse direction. As a result, the event information for 1, sentence 01-R2 is found. Further, by tracing the event information in the reverse direction from this event information, the event information for pin R2 is determined. Here, due to the network structure, sentence 01-R2 and pin R
When we examine the connection relationship of 2, we find that it is a data type connection.

Therefore, it can be seen that data is first propagated from pin R2 to pin 01 via the line 01-R2. Next, by tracing the event information of pin R2 in reverse, the event information of sentence R2-Tl and the event information of pin CLKI are found.

Here, depending on the network structure, statement 1?2- Tl and pin CLK
Examining the connection relationship of l, it is found that it is a clock system connection. Here, it can be seen from the network structure that there is pin T1 as a pin having a data system connection for sentence R2-TI. Event information (Tl<0:3>, 4BIO11, 50) is obtained by searching for event information for pin Tl having a time closest to the event occurrence time of sentence R2-Tl. Therefore, it can be seen that data is propagated from pin Tl to pin R2 via statement R2-TI.

Next, by tracing the event information of pin T1 in reverse,
Event information for the sentence TI-^DD (1?1. IBI, l old) and pin R1 can be found. here,
Go to statement Tl- by network structure〇〇(R1, IBI, IDI)
Examining the connection relationship between pin CLK1 and pin CLK1, it is found that the connection is for the data system. Therefore, it can be seen that data is propagated from pin R1 to pin TI via the statement Tl-^DD (R1, lB1.1B1). Furthermore, by tracing the event information of pin R1 in reverse, event information of sentence R1-DI and event information of pin CLKI are found. here,
According to the network structure, the sentence Tl -ADD(R1゜lB1.IBl
) and pin CLKI, it is found that they are clock system connections.

Here, in the same way, from pin DI to pin R1, the sentence 1?1-
It can be seen that data propagates through the old. Old is the input bin, so the search ends here. Furthermore, the search method when there is a control system connection can be performed in substantially the same way as in the case of a clock system.

FIG. 7 shows a route searched using the event information shown in FIG. 6 and the network structure shown in FIG. Not only the order of the pins, but also the exact signal propagation path can be determined by providing sentence information. It is also useful for verifying logic circuits because it can also display pin values.

Note that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof. In the embodiment, the route was searched by focusing on the flow of data signals in the circuit, but it is also possible to search for the route by focusing on the control signal or clock signal.

[Effects of the Invention] As detailed above, according to the present invention, it becomes possible to use a computer to search for the propagation path of a signal inside a circuit, which was conventionally done manually, and the scale of the logic circuit becomes large. However, it is possible to easily trace the signal flow inside the circuit, and it is possible to improve the verification efficiency of the logic circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a route extraction device according to an embodiment of the present invention, FIG. 2 is a flowchart for explaining a route extraction method using the above device, and FIG. 3 is a R
A diagram showing the logic circuit description of TL, FIG. 4 is a diagram showing the network structure of the logic circuit description shown in FIG. 3, and FIG. 5 is a test pattern for verifying the logic circuit description shown in FIG. 3. FIG. 6 is a diagram showing an example, and FIG. 6 is a diagram showing event information and connection relationships created when a simulation is performed using the network structure shown in FIG. 4 and the test pattern shown in FIG. 5. This figure shows the results of route searching using the network structure shown in FIG. 3 and the event information shown in FIG. 6. 10... Execution control section, 11... Description creation section, 12... Network structure extraction section, 13... Simulation execution section, 14... Expected value comparison section, 15... Route extraction section.

Claims (1)

[Claims] (1) Extract the network structure of the circuit to be simulated from the logic circuit description written in the logic circuit design description language, perform an event-driven logic circuit simulation based on the network structure and the test pattern, and A route extraction method, characterized in that a route activated by the test pattern is extracted by using information and the network structure. (2) A network structure extraction unit that extracts the network structure of the circuit to be simulated from the logic circuit description written in the logic circuit design description language, and a logic circuit using the network structure and test pattern extracted by this network structure extraction unit as input. An event-driven simulator that performs circuit simulation and outputs information on events that have occurred, and is activated by the test pattern based on the event information output from this simulator and the network structure extracted by the network structure extraction section. 1. A route extracting device, comprising: a route extracting unit that extracts a route that has been extracted.