JPH0261742A - Peripheral controller - Google Patents

Abstract

PURPOSE:To reduce the load on a microprocessor to shorten the processing time by changing addressing to transfer data from the host system bus side to the peripheral system bus side. CONSTITUTION:A microprocessor on the host side writers data in an input register 4. At this time, data of the lower address and data of the upper address are written in the upper part and the lower part of the register 4 respectively. The host side instructs a screen controller 1 by a command to output data written in the register to a bus on the peripheral side. The screen controller 1 takes data inputted to the input register 4 into a data converting circuit 2 and converts data in accordance with a control signal 3. Data is outputted from an output buffer 5 to the area indicated by an address generator of the picture controller 1.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to peripheral controllers.

[Prior Art] In recent microprocessor systems, system buses having 16 bits or more are increasingly being used as microprocessors become more multi-functional and high-performance. However, most memories in current systems are addressed in units of 1 byte (=8 bits). As a result, for example, when looking at a system with a 16-bit system bus, depending on the nature of the microprocessor, there are cases in which odd addresses are assigned to the upper byte of the system bus (see Figure 2 (a)) and cases in which even addresses are assigned to the upper byte. The method of address allocation is different from the case of allocation (see Figure 2 (b)).
There is a street system.

On the other hand, some peripheral controllers such as image controllers have a function of transferring data from the system bus side to the image memory bus side through the peripheral controller itself. At this time, with conventional peripheral controllers, even if the address assignment method described above is different between the system bus side and the image memory bus side, the address assignment remains the same as that when input from the system bus side to the peripheral controller. It was outputting to the side. For this reason, the host-side microprocessor executes instructions from the host-side microprocessor to exchange the upper byte and the lower byte.

[Problems to be Solved by the Invention] As mentioned above, in conventional peripheral controllers, if the address allocation method described above is different between the host system bus side and the peripheral system bus side, the microprocessor on the host side By executing the microprocessor's instructions, the upper byte and lower byte must be exchanged, so the larger the amount of data, the more time it takes to process the data, and the greater the burden on the microprocessor. It has the disadvantage of being

[Differences and Originality of the Invention from the Prior Art] In contrast to the above-mentioned conventional peripheral controllers, the present invention provides a method for transferring data from the host system bus side to the peripheral system bus side through the peripheral controller itself. , which has the original content of changing address allocation.

[Means for Solving the Problems] The peripheral controller of the present invention is a peripheral controller that transfers data from the host system bus side to the peripheral system bus side by passing through itself, and the first peripheral controller to which data is written from the host system bus side. means, a second means for dividing the data stored in the first means into m bits of 2 or more to form n bit groups, and rearranging the order of the bit groups; and a signal group for controlling the second means.

[Example code] Next, the present invention will be explained through examples.

FIG. 1 is a diagram showing an embodiment of the present invention. In this embodiment, an image controller is shown as a peripheral controller. An actual image controller includes a drawing circuit, a display circuit, etc., which are not shown, but these are omitted in the figure because they are not directly related to the present invention.

In the figure, the left side is called the host side, and the right side is called the peripheral side.

In this example, the data buses on both the host side and the peripheral side are 16 bits, and the host side has the address allocation shown in Figure 2(a), and the peripheral side has the address allocation shown in Figure 2(b). It is assumed that

Image controller 1 is an image controller according to the invention. The data conversion circuit 2 is a circuit that converts data input from the input register 4 in accordance with the control signal 3. The control signal 3 is a signal for controlling whether or not the upper byte and lower byte of the data input from the input register 4 are exchanged. The output buffer 5 is a buffer for outputting the data converted by the data conversion circuit 2 to the peripheral bus side.

Next, the operation will be explained.

The microprocessor on the host side is given a control signal 3 in advance according to the address allocation method between the host side and the peripheral side. The control signal 3 can be generated by giving it as a hardware signal from the host side, giving it as a software signal like a command, etc., but this is not specified in the present invention.

The microprocessor on the host side writes data to the manual register 4. At this time, in the figure, it is assumed that the data of the lower address is written in the upper part of the manual register 4, and the data of the higher address is written in the lower part.

Next, the microprocessor on the host side instructs the image controller 1 by a command or the like to output the data written in the manual register 4 to the peripheral side bus. The image controller 1 takes the data input into the input register 4 into the data conversion circuit 2, and converts the data according to the control signal 3. In this embodiment, the upper 8 bits and lower 8 bits of the data are exchanged and input to the output buffer 5 manually.

Data is output from the output buffer 5 to an area indicated by an address generated by an address generator (not shown) inside the image controller 1. At this time, in this embodiment, the data of the upper address is output from the upper side of the output buffer 5, and the data of the lower address is output from the lower side.

In this embodiment, when the addresses shown in FIG. 2(a) are assigned to both the host side and the peripheral side, the data inputted manually to the data conversion circuit 2 in the above explanation is transferred to the control signal 3.
Therefore, the operation is the same except that the data on the upper side and the data on the lower side are not interchanged. The effects of the invention can be fully explained in this example.

[Effects of the Invention] As described above, according to the present invention, even if the above-mentioned address assignment methods are different between the host system bus side and the peripheral system bus side, the system bus side Since the data input to the peripheral controller is output from the host system bus side to the peripheral system bus side, the data can be passed through the peripheral controller from the host system bus side without the host side microprocessor executing data conversion according to instructions from the host side microprocessor. This has the effect of allowing data transfer to the peripheral system bus side.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an address map diagram when even and odd addresses are allocated to upper bytes and lower bytes in a memory. 1 ・ 2 φ 3 ・ 4 ・ 5 ・ Image controller, data conversion circuit, control signal, input register, output buffer. Patent applicant: NEC Corporation

Claims (1)

[Claims] In a peripheral controller that transfers data from the host system bus side to the peripheral system bus side, a first means to which data is written from the host system bus side, and data stored in the first means are written in two or more m bits each. A peripheral controller comprising: a second means for rearranging the order of the bit groups; and a signal group for controlling the first means and the second means. .