JPH0261145B2 - - Google Patents
Info
- Publication number
- JPH0261145B2 JPH0261145B2 JP56048584A JP4858481A JPH0261145B2 JP H0261145 B2 JPH0261145 B2 JP H0261145B2 JP 56048584 A JP56048584 A JP 56048584A JP 4858481 A JP4858481 A JP 4858481A JP H0261145 B2 JPH0261145 B2 JP H0261145B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- single crystal
- annealing
- axis
- energy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000013078 crystal Substances 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 9
- 238000003776 cleavage reaction Methods 0.000 claims description 5
- 230000007017 scission Effects 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 34
- 238000005468 ion implantation Methods 0.000 description 3
- 230000001678 irradiating effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000000348 solid-phase epitaxy Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Optics & Photonics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明は単結晶ウエハーのアニーリング方法に
係り、特にアニーリングによる単結晶ウエハーの
割れを防止するようにした単結晶ウエハーのアニ
ーリング方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for annealing a single crystal wafer, and more particularly to a method for annealing a single crystal wafer to prevent cracking of the single crystal wafer due to annealing.
イオン打込みによつて損傷を受けたシリコン単
結晶ウエハーの表面に高出力のレーザ光、イオン
ビーム、電子線等のエネルギー線を照射すること
によつて、該単結晶ウエハー面上の損傷が結晶回
復することはよく知られている。即ちエネルギー
線がパルスレーザを用いる場合のアニーリングの
メカニズムはウエハー面上の温度が融解点まで上
昇し、再結晶化する液晶エピタキシーであり、
CWレーザを用いる場合はウエハー温度は融解温
度まで達せずに再結晶化する固相エピタキシーの
概念を用いて説明されている。 By irradiating the surface of a silicon single crystal wafer damaged by ion implantation with energy beams such as high-power laser beams, ion beams, and electron beams, the damage on the surface of the single crystal wafer is recovered. It is well known to do so. That is, when a pulsed laser is used as the energy beam, the annealing mechanism is liquid crystal epitaxy in which the temperature on the wafer surface rises to the melting point and recrystallizes.
When using a CW laser, the wafer temperature is explained using the concept of solid-phase epitaxy, in which recrystallization occurs before the wafer temperature reaches the melting temperature.
更に上記した単結晶ウエハー面上のイオン打ち
込みによる結晶損傷だけでなく、予め単結晶ウエ
ハー面上にCVD法等で形成した多結晶層や真空
蒸着等で非晶質のシリコン層を形成した面にエネ
ルギー線を照射することで多結晶層又は非晶質層
を単結晶化し得ることも知られている。 Furthermore, in addition to crystal damage caused by ion implantation on the surface of a single crystal wafer as described above, damage to a polycrystalline layer previously formed on the surface of a single crystal wafer by CVD or an amorphous silicon layer formed by vacuum evaporation, etc. It is also known that polycrystalline or amorphous layers can be made into single crystals by irradiating them with energy rays.
又、単結晶シリコンウエハー表面にドーピング
を行なうためイオン・インプランテーシヨンと同
時にアニーリングを行なう技術も良く知られてい
る。 Also, a technique of performing annealing simultaneously with ion implantation in order to dope the surface of a single crystal silicon wafer is well known.
上述の如き、単結晶ウエハー又は非晶質層或は
多結晶層の形成されたウエハー表面(以下ウエハ
ーと記す)にエネルギー線を照射する際に従来の
構成に於ては、第1図示の如くXYステージ1上
に構成されたウエハー2にはフアセツト面3が形
成されMOS用のウエハー等では面方位が(100)
のものが用いられている。 When irradiating an energy beam onto a single crystal wafer or a wafer surface (hereinafter referred to as wafer) on which an amorphous layer or a polycrystalline layer is formed as described above, in the conventional configuration, as shown in the first diagram, A facet surface 3 is formed on the wafer 2 configured on the XY stage 1, and in the case of wafers for MOS, the surface orientation is (100).
are used.
4はレーザ等のエネルギー線源で該エネルギー
線源よりの熱エネルギーはプリズム5及びレンズ
6で反射、集光され、ウエハー2上に焦点スポツ
ト7を形成し、ウエハー2表面を融解させる。 Reference numeral 4 denotes an energy ray source such as a laser. Thermal energy from the energy ray source is reflected and focused by a prism 5 and a lens 6 to form a focal spot 7 on the wafer 2 and melt the surface of the wafer 2.
上述の構成でXYステージ1に載置されたウエ
ハー2はフアセツト面3をXYステージY−Y軸
方向又はX−X軸方向と平行になる様に正確に固
定される。 The wafer 2 placed on the XY stage 1 with the above configuration is accurately fixed so that the facet surface 3 is parallel to the Y-Y axis direction or the X-X axis direction of the XY stage.
この状態で焦点スポツト7を固定状態として、
XYステージ1をX−X軸又はY−Y軸方向に動
かせば叙上のウエハー2では面方位(100)の<
110>方向に平行に走査8がなされることになる。
即ち走査はフアセツト面3に平行又はこれと直交
する方向になされる。 In this state, with the focal spot 7 fixed,
By moving the XY stage 1 in the X-X axis or Y-Y axis direction, the surface orientation (100) of the above wafer 2
A scan 8 will be performed parallel to the 110> direction.
That is, scanning is performed in a direction parallel to or perpendicular to the facet plane 3.
このような(100)ウエハーに於ては特に<110
>方向が劈開し易い性質を持つており、エネルギ
ー線の照射によつてウエハー表面が融解すると共
に急激な冷却によつて単結晶化される際に<110
>方向に平行に残留熱歪があると、更にウエハー
は破損し易い欠点を生ずることを見出した。特に
上述したウエハー表面のエネルギー線照射後の熱
処理工程、ハンドリング工程でウエハーの破壊、
破損は著しく増大する。 Especially for such (100) wafers <110
The wafer surface is melted by energy ray irradiation and is rapidly cooled to become a single crystal.
It has been found that residual thermal strain parallel to the > direction also causes the wafer to be easily damaged. In particular, the wafer may be destroyed during the heat treatment process and handling process after the wafer surface is irradiated with energy rays.
Damage increases significantly.
本発明は上述の欠点を除去した単結晶ウエハー
のアニーリング方法を提供するものであり、その
特徴とするところはアニーリングに際して、劈開
し易い方向とは22.5゜乃至67.5゜ずれた方向にエネ
ルギー線を走査させるようにして残留熱歪による
ウエハーの劈開を防止するようにしたものであ
る。 The present invention provides a method for annealing single crystal wafers that eliminates the above-mentioned drawbacks, and is characterized in that during annealing, an energy beam is scanned in a direction that is deviated by 22.5° to 67.5° from the direction in which cleavage is likely to occur. In this way, cleavage of the wafer due to residual thermal strain is prevented.
以下本発明の1実施例を第2図及び第3図につ
いて詳記する。 An embodiment of the present invention will be described in detail below with reference to FIGS. 2 and 3.
第2図に示すものは第1図に示すXYステージ
を上方よりみた平面図でありXYステージ1上に
(100)面方位の単結晶ウエハー2を載置して固定
する際にフアセツト面3と直交する軸F−FとX
−X軸又はY−Y軸間に角度θを持たせて取り付
ける。 What is shown in FIG. 2 is a plan view of the XY stage shown in FIG. Orthogonal axes F-F and X
- Install with an angle θ between the X-axis or Y-Y axis.
角度θ=45゜であればシリコンウエハー2の面
方位が(100)の場合にX−X軸及びY−Y軸は
<110>方向となり、この方向は結晶学的にも劈
開し難い方向となる。 If the angle θ = 45°, when the plane orientation of the silicon wafer 2 is (100), the X-X axis and the Y-Y axis will be in the <110> direction, and this direction is also considered to be a direction in which cleavage is difficult from a crystallographic point of view. Become.
このため、エネルギー線の焦点スポツト7をX
軸及びY軸方向に(<100>に平行な方向)に走
査しても後処理工程のハンドリング等でウエハー
を破損させることはない。 For this reason, the focus spot 7 of the energy beam is
Even if the wafer is scanned in the axial and Y-axis directions (direction parallel to <100>), the wafer will not be damaged during handling in the post-processing process.
上述の角度θ=22.5゜〜67.5゜の値をとつても<
110>方向に比べて破損を大巾に減少し得て製作
工程の歩留を向上し得る。 Even if we take the above angle θ = 22.5° to 67.5°, <
Compared to the 110> direction, damage can be greatly reduced and the yield of the manufacturing process can be improved.
第2図はスポツト7を固定しXYステージ1を
X−X,Y−Y軸方向に動かして走査7を行つた
が、第3図に示す如く、フアセツト面3と直交又
は平行な軸Y−Y軸、X−X軸と角度θを有する
<100>方向と平行な方向にエネルギー線側を動
かして走査を行つた場合である。 In FIG. 2, scanning 7 was performed by fixing the spot 7 and moving the XY stage 1 in the X-X, Y-Y axis directions, but as shown in FIG. This is a case where scanning is performed by moving the energy beam side in a direction parallel to the <100> direction having an angle θ with the Y axis and the X-X axis.
勿論この場合もθ=22.5゜〜67.5゜に選択し得る
は明らかである。 Of course, in this case as well, it is obvious that θ=22.5° to 67.5° can be selected.
本発明は上述の如くエネルギー線の走査方向を
劈開し易い方向とずれた方向に走査させたためエ
ネルギー線の照射によつて熱的な歪がウエハー1
上に残つても破損されるようなことはなくなり、
初期の目的であるアニーリングによる単結晶化や
ドーピング等を行なうことが出来る特徴を有する
ものである。 As described above, in the present invention, the scanning direction of the energy beam is shifted from the direction in which cleavage is likely to occur, so that thermal distortion is caused by the irradiation of the energy beam on the wafer.
Even if it remains on top, it will not be damaged,
It has the characteristic that it can perform the initial purpose of single crystallization by annealing, doping, etc.
第1図は従来の単結晶ウエハーのアニーリング
方法を示す斜視図、第2図は本発明のウエハーの
アニーリング方法の一実施例を示す平面図、第3
図は本発明の他の実施例を示す第2図と同様の平
面図である。
1……XYステージ、2……ウエハー、3……
フアセツト面、4……エネルギー線源、5……プ
リズム、6……レンズ、7……焦点スポツト、8
……走査線。
FIG. 1 is a perspective view showing a conventional method for annealing a single crystal wafer, FIG. 2 is a plan view showing an embodiment of the wafer annealing method of the present invention, and FIG.
This figure is a plan view similar to FIG. 2 showing another embodiment of the present invention. 1...XY stage, 2...wafer, 3...
Facet surface, 4... Energy ray source, 5... Prism, 6... Lens, 7... Focal spot, 8
...scanning line.
Claims (1)
至67.5゜ずれた方向にエネルギー線を走査してな
る単結晶ウエハーのアニーリング方法。1. A method of annealing a single crystal wafer in which an energy beam is scanned in a direction deviated by 22.5° to 67.5° from the cleavage direction of the semiconductor single crystal wafer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4858481A JPS57162434A (en) | 1981-03-31 | 1981-03-31 | Annealing method for single crystal wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4858481A JPS57162434A (en) | 1981-03-31 | 1981-03-31 | Annealing method for single crystal wafer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57162434A JPS57162434A (en) | 1982-10-06 |
JPH0261145B2 true JPH0261145B2 (en) | 1990-12-19 |
Family
ID=12807444
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4858481A Granted JPS57162434A (en) | 1981-03-31 | 1981-03-31 | Annealing method for single crystal wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57162434A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4927778A (en) * | 1988-08-05 | 1990-05-22 | Eastman Kodak Company | Method of improving yield of LED arrays |
JP5614739B2 (en) * | 2010-02-18 | 2014-10-29 | 国立大学法人埼玉大学 | Substrate internal processing apparatus and substrate internal processing method |
JP6119712B2 (en) * | 2014-10-08 | 2017-04-26 | トヨタ自動車株式会社 | Manufacturing method of semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55150238A (en) * | 1979-05-10 | 1980-11-22 | Matsushita Electric Ind Co Ltd | Method of irradiating laser beam |
-
1981
- 1981-03-31 JP JP4858481A patent/JPS57162434A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55150238A (en) * | 1979-05-10 | 1980-11-22 | Matsushita Electric Ind Co Ltd | Method of irradiating laser beam |
Also Published As
Publication number | Publication date |
---|---|
JPS57162434A (en) | 1982-10-06 |
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