JPH0258926A - D/a converter - Google Patents

Abstract

PURPOSE:To compose a D/A converter with high accuracy by dividing input digital data into plural pieces, using respectively three ROMs, adders and D/A converters and, further, using an analog adder. CONSTITUTION:The title converter is equipped with ROMs 1-3, digital adders 4-6, D/A converters 7-9 and an analog adder 10, and inputted digital data 11 [D0(LSB)-Dn(MSB)] are divided into low-order bit signals D0-D1, middle order bit signals D1+1-Dm and high-order bit signals Dm+1-Dn (0<l<m<n, n<2). When respective outputs of the D/A converters 7-9 are analog-added by the analog adder 10, an analog output 12 to the input digital data 11 is obtained. Thus, the D/A converter with high accuracy can be obtained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a DA converter.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional example.

13 is) i, OM, 14 is an adder, 15.16 is a 0 person converter, 17 is an analog adder, 18 is an analog output, 1
9 is digital input data (Do-Dm.

Dm+t~I)1:n>m>0, n>1).

The operation of the DA converter shown in FIG. 2 will be explained.

D0 (LSB) to D of input digital data 19
n(MSB)'i First Do-DIn and Dm+ l~D1
Divide into Dm+l-D, connected to the digital input of the ViDA converter 15 and the address input of the ROM 13; D
.

The outputs of ~Dm and ROM13 are respectively connected to two sets of inputs of the adder 14, and the output of the adder 14 is connected to the digital input of the DA converter 16.

The outputs of the DA converters 15 and 16 are added by an analog adder 17. When adding, the thickness of the minimum resolution (ILsB) of the DA converter 15 and the DA converter 16 is set to be in a ratio of 2m+1:1 when being added.

Here, the data stored in the ROM13 is designed to be able to output data for all of the input digital data from Drn+l to Dfl, and the error of the DA converter 15 is measured in advance, and its correction value is stored in the R,0M13. , and the output of Do-Dm of the input digital data, the output of the DA converter 16 can be a combination of the output corresponding to Do-Dffl and a value that cancels out the error of the DA converter 15.

[Problem to be solved by the invention]

The conventional ODA converter described above divides the input digital data into two and performs correction and conversion, but as the number of input bits of digital data increases, the ROM capacity increases.
A high resolution of the A converter is required. Each time the data increases by 1 bit, the ROM capacity 9 resolution doubles, so if a multi-bit D/A converter is implemented using conventional technology, the number of elements will increase, and the ROM capacity for correction will also increase. The disadvantage is that it requires a lot.

[Means to solve the problem]

The ODA converter of the present invention has lower bit signals D0 (LSB) to Dl, middle bit signals DI+I to Dml, and upper bit signals Drn+l to L.
). (B) a first ODA converter that performs DAi conversion on the upper bit signal of an n-bit input signal consisting of (MSB) and outputs an upper analog signal; (B) the first DA conversion based on the upper bit signal; The first part corresponding to the middle (i)1+1~Dm) part of the error correction data of the instrument
a first ROM that outputs a correction signal;

(G) a first adder that adds the intermediate bit signal and the first correction signal and outputs a first addition signal; (D)
Based on the upper bit signal, the lower order (D) of the error correction data of the first ODA converter is determined.

(LSB) to Dt), a second ROM that adds the lower bit signal and the second correction signal, and outputs a second addition signal; (machi) A second ODA converter that performs DA conversion on the second addition signal and outputs an intermediate analog signal, p) Error correction data of the second ODA converter based on the second addition signal. A third ROM outputting a third correction signal.

a third adder that adds the second addition signal and the third correction signal and outputs the third addition signal; (1) DA converts the third addition signal and converts the third addition signal to a lower analog signal; a third DA converter for outputting (J) the minimum resolution of each of the upper, middle, and lower analog signals of 2. 2. 1 and an analog adder that adds the signal to 1 and outputs a final conversion signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

1.2.3 is ROM, 4, 5.6 is digital adder 7
, 8.9 is a DA converter, 10 is an analog adder, 11 is a digital input Do-Dn, and 12 is an analog output.

The present invention will be described in detail.

Input digital data 11. Do(LSB)～Dn
(M8B), Do-DZ, DI+I ~Dm, Dm+
I-D.

(o<l<m<n, n>2).

Dm+l to Dn are connected to the digital input of the DA converter 7 and the RO
Connect to address inputs of M1 and 'fLOM2. 0
The human converter 7 directly outputs an analog value corresponding to the digital data of Dm+1'-Dn.

A DA converter 7 is installed in advance for ROMI, R, 0M2.
Write the data to correct the error. ROM1
The upper part (corresponding to D/+l to Dm) of the input digital data 11 out of the correction data of the DA converter 7 is read out from the DA converter 7, and is added to the value of Dl+t −D□ by the adder 4. . Although it appears that only addition is possible here, subtraction is also possible if the correction data is expressed in complement form.

The output of the adder 4 is connected to the DA converter 8 and the address of the ROM 3. Here, the DA converter 8 converts the input digital data 11 into DI! an analog value corresponding to +t-Dm,
A value for correcting the error of the DA converter 7 is also output.

A correction value for the error of the DA converter 8 is written from the ROM 3. The data on the lower side (corresponding to Do-Dj) of the correction value of the DA converter 7 is read from the ROM 2, and the adder 5 reads Do-DI! of the input digital data 11. is added. Furthermore, the adder 6 adds the correction value of the DA converter 8, and the DA converter 9 converts it into an analog value.

Finally, the analog adder 10 converts the DA converter 7, DA
Add the outputs of converter 8 and DA converter 9 (analog addition)
If you do this, the input digital data 11 Do” Dn
An analog output 12 is obtained for.

The weighting of the DA converter output may be done by each DA converter, or by weighting by 1:2Z+1.2 during addition.
It is also possible to add it to the weight of

〔Effect of the invention〕

As explained above, the present invention divides input digital data into a plurality of parts, and uses three ROMs, adders, and DA converters each.
Furthermore, by using an analog adder, a highly accurate A converter can be constructed.

To specifically express the effects of the present invention, assume that the input digital data t'' is 12 bits, for example.

Conventional example f) A converter 1 resolution 1/64 (6 bits DA converter 2 resolution 1/128 + 6 bits) (with digit raising by adder) ROM capacity 64 (address) x 6 (data width): 384 bits DA Converter 1 resolution 1/16 DA converter 2 resolution 1/32 (Adder 1 digits included) DA converter 3 resolution 1/64 (Adders 2 and 3 digits included) ROM capacity ((16 (address) ) × 2) + 32 (address)) When using a resistor string method, a resistor is required corresponding to the resolution. Therefore, if we simply compare the number of resistors, the conventional example has 192 resistors.
M capacity 384 bits, 112 inventive resistors, ROM capacity 2
If the input data is 18 bits, the number of resistors in the conventional example is 51 (divided into 9 bits + 9 pits).
2 + 1024 = 1536 lines R, OM capacity is 512 (address) x 9 (data width) = 4608 bits, in the present invention (divided into 6 bits + 6 bits + 6 bits) the number of resistors is 64 + 128 + 256 = 448 lines, ROM capacity is (( 6
4X2)+128(address))X6(data width)=1
As the number of bits of the input digital data increases, such as 536 bits, the effect of the present invention becomes more pronounced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 1.2, 3.13...ROM. 4, 5, 6.14... Adder, 7.8, 9, 15.16... DA converter, 10.17... Analog adder, 11.19... Digital input.

Claims (1)

[Claims] (A) Lower bit signal D_0 (LSB) to D_1, middle bit signal D_1_+_1 to D_m, upper bit signal D
(B) a first DA converter that performs DA conversion on the upper bit signal of an n-bit input signal consisting of _m_+_1 to D_n (MSB) and outputs an upper analog signal; Middle of the error correction data of the first DA converter (D_1_+_1 to D_m)
a first ROM that outputs a first correction signal corresponding to the portion
(C) a first adder that adds the middle bit signal and the first correction signal and outputs a first addition signal; (D) a first adder that adds the middle bit signal and the first correction signal and outputs a first addition signal;
The lower order (D_0(LSB) of the error correction data of the A converter
) to D_1), (E) a second ROM that adds the lower bit signal and the second correction signal and outputs a second addition signal; an adder; (F) a second DA converter that performs DA conversion on the second addition signal and outputs an intermediate analog signal; (G) a second DA converter that converts the second addition signal into an intermediate analog signal;
a third ROM that outputs a third correction signal that is error correction data of the A converter; (H) adds the second addition signal and the third correction signal and outputs a third addition signal; a third adder; (I) a third DA converter that performs DA conversion on the third addition signal and outputs a lower analog signal; (J) minimum resolution of each of the upper, middle, and lower analog signals; The size of is 2^m^+^1:2^1^+^1
A DA converter characterized by comprising: an analog adder that adds the total value to 1 and outputs a final converted signal.