JPH0258921A - Multiplexer - Google Patents

Abstract

PURPOSE:To speed up a processing by using a three-stage latch type D type flip-flop instead of a two-stage latch type D type flip-flop in a master slave type. CONSTITUTION:The title multiplexer is provided with D type flip-flop DFFs 1 and 2, a selecting circuit SELECTOR 3 to selectively output data signals inputted to data signal input terminals D1 and D2 by the 'H' level or 'L' level of a selecting signal Se inputted to a selecting signal input terminal S, and a delaying circuit DELAY 4 for adjusting a timing. Instead of the conventional two-stage latch type DFF in the master slave type, the constitution is executed by using the three-stage latch type DFF. Consequently, the timing margin of the selecting signal is enlarged, and an output signal without a malfunction can be obtained from the selecting circuit 3. Thus, a high-speed operation can be realized.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multiplexer that converts parallel signals input from two channels into serial signals, and particularly relates to a circuit configuration suitable for high-speed operation. .

[Conventional technology]

FIG. 3 shows an example of the circuit configuration of a general multiplexer.

In the same figure, ■, 2 is a D-type flip-flop (DFF) consisting of two latches, a master and a slave.
, 3 are data signal input terminals DI depending on the level (“H” level or rLJ level) of the selection signal Se input to the selection signal input terminal S.

A selection circuit (SELECTOR) selects and outputs a data signal input to D2, and 4 is a delay circuit (DELAY) for timing adjustment.

Signal input terminal 5. The data signals Ai, Bi (i=0.1, 2.3...-) input from the signal input terminal 6 are input to each of DFFI and DFF2 at the falling edge of the clock signal C input from the input terminal 7. Output from output terminals Ql and Q2. SELECT these output signals
When the selection signal Se input to the selection signal input terminal S of 5ELECTOR3 (this has a different timing from the clock signal C) is at the rLJ level, the signal input to the data signal input terminal D1 is input to OR3. ,
At rHJ level, the signal input to the data signal input terminal D2 is selected and a serial signal of data signals Ai and Bi is output from the output terminal Q3 of the 5ELECTOR 3 to the output terminal 8.

FIG. 5 shows signal waveforms of various parts showing the operation of this circuit configuration. However, the delay time of each circuit is ignored.

In the figure, the clock signal C ((a) in the figure) input to the clock input terminals CL of DFFI and DFF2 causes
Signal strings Ai and Bi ((b) and (c) in the figure) are outputted from the output terminals Ql and Q2 of DFFI and DFF2, respectively, and these are input to the data signal input terminal DI of 5ELECTOR3.

Input to D2. At this time, a delay equal to the signal delay occurring in DFFI and DFF2 is applied to the clock signal C by DELAY4, and this is inputted to the selection signal input terminal S as the selection signal Se ((d) in the figure) of 5ELECTOR3. When the selection signal Se is at rLJ level, the terminal DI
When the data signal Ai input to the terminal D2 is at the rHJ level, the signal Bi input to the terminal D2 is selected.
), the data signals Ai and Bi input to the terminals Di and D2 are alternately output from the output terminal Q3.

[Problem to be solved by the invention]

As explained above, by using the circuit having the configuration shown in FIG. 3, two parallel signals can be converted into one serial signal. However, the above explanation is an ideal case, and the reality is different. That is, the delay times of DFF1 and DFF2 are not equal, and even if they were equal, it would be impossible to create a delay time completely equal to the delay time in DELAY4. Furthermore, the signal has a finite rise and fall time - these times are not equal for boat fishing. Therefore, the time Ta shown in FIG.
, Tb, and Ts cannot be made to match completely. Therefore, the data in the portion of the output signal of the 5ELECTOR 3 ((e) in the figure) shown by the arrow becomes extremely unstable, resulting in a problem of malfunction.

FIG. 6 shows a specific example of this malfunction, and shows the data signal Ai(
This shows a case where (a) in the figure and the data signal Bi ((b) in the figure) are in phase, but the selection signal Se ((C) in the figure) is delayed. In this case, a malfunction will occur in the area indicated by the arrow, as shown in (d) in the figure.

In order to solve this problem, conventionally, the serial data signal of (e) in FIG.
F3 (not shown in Figure 3), and input it to Figure 5 (
Transfer the data from the master section to the slave section at the rising edge of the clock signal C2 (twice the frequency of (a)) in f),
It was configured to output a shaped waveform as shown in (g). However, with this configuration, the time that the data does not change before the clock rises in DFF3 (when the data is Ai) and the time that the data does not change after the clock rises (when the data is BiO) are shortened. , it is difficult to increase the speed.

An object of the present invention is to realize a multiplexer capable of high-speed operation by eliminating malfunctions caused by unstable operation inherent in conventional circuits.

[Means to solve the problem]

In order to achieve this object, the present invention uses a three-stage latch-type D-type flip-flop in place of the conventional master-slave two-stage latch-type D-type flip-flop.

[For production]

The timing margin of the selection signal output from the selection circuit with respect to the data signal becomes large.

〔Example〕

Next, one embodiment of the present invention will be described in detail below with reference to FIGS. 1 to 4.

The configuration of this embodiment is shown similarly to FIG. 3, and the difference from the conventional configuration in the figure is that the two-stage latch DFF
The difference is that a three-stage latch D-type flip-flop is used instead.

This three-stage latch D type flip-flop (hereinafter referred to as 3
-DFF) is shown in the equivalent circuit diagram of Fig. 1. Another latch is connected after the two-stage latch of the conventional two-stage D-type flip-flop shown in Fig. 2. This constitutes a three-stage latch.

In FIG. 1, VDD is a ground terminal, VSS is a power supply terminal, and VCS is a current source terminal. Also, DT is a data input terminal, DC is its reference terminal or reverse phase signal input terminal, CT is its clock input terminal, CC is its reference terminal or reverse phase signal input terminal, QIT is its output terminal, and QIC is its reverse phase signal output. The terminals Q2T and Q2C are signal output terminals obtained by shifting the level of QIT and QIC by one diode, respectively. In addition, although J and s in the same figure show cases where FETs are used as transistors, ECLs using ordinary bipolar transistors in the same way
(Emitter Coupled Logic)
The same applies to the case of .

When this 3-DFF is used instead of the conventional DFF2,
The following operational differences arise: In other words, in the conventional master-slave type D-type flip-flop, when the clock falls, the data written to the master moves to the slave and becomes the output of the D-type flip-flop, but in the 3-DFF, the clock When rising, data moves to the third stage latch and becomes the output of the 3-DFF. Therefore, the operating waveforms of each part in the configuration of this embodiment in which the 3-DFF is used in place of the DFF2 are as shown in FIG.

In the figure, a clock signal (a) is commonly input to each clock terminal CL of DFF1 and DFF2, and
The data signal Ai ((b) in the figure) output from F1 and the data signal Bi ((C) in the figure) output from DFF2 using a 3-DFF are shifted by a half cycle. Therefore,
By applying the selection signal Se as shown in (d),
The timing margin of the selection signals S and e is large, about half a cycle, so as the output of 5ELECTOR3 (e)
As shown in Figure 2, a signal without any instability can be obtained.

In addition, even if a D-type flip-flop is installed next to 5ELECTOR3 to perform retiming, as in the conventional case, the timing margin between the clock signal and data signal will not be as small as in the conventional circuit configuration, and will be stable. This has the great effect of making it possible to realize circuit operation.

In addition, in the above explanation, the operation of a flip-flop is expressed as, for example, D
Although the output of the FFI is assumed to change at the falling edge, it is completely free to design whether the output of the flip-flop is changed at the rising edge or at the falling edge, and the present invention is effective in either combination. That is clear.

〔Effect of the invention〕

As explained above, the present invention replaces the conventional two-stage master-slave type D-type flip-flop with three
By using a staged latch type D-type flip-flop, the timing margin of the selection signal output from the selection circuit with respect to the data signal becomes large.

In other words, in the conventional multiplexer, it was essential to provide a D-type flip-flop next to the selection circuit in order to avoid malfunction of the output signal of the selection circuit, but when the two data signals input to the selection circuit Since there is no timing margin between the selection signal and the selection signal, the timing margin between the clock signal and data signal of the D type flip-flop is small in this case as well, making it difficult to increase the speed.

However, according to the present invention, as described above, the timing margin of the selection signal is increased, and an output signal without malfunction can be easily obtained from the selection circuit.

Furthermore, even in the circuit configuration according to claim 2 of the present invention, that is, the configuration in which a D-type flip-flop is provided next to the selection circuit to perform retiming, the timing margin between the clock signal and the data signal is the same as in the conventional circuit configuration. This has the effect of realizing stable circuit operation without becoming too small.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram of a D-type flip-flop using three latches applied to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a conventional D-type flip-flop using two latches. Fig. 3 is a block diagram showing the circuit configuration of a general multiplexer, Fig. 4 is an operating waveform diagram of a multiplexer according to an embodiment of the present invention, Fig. 5 is an operating waveform diagram of a conventional multiplexer, and Fig. 6 is a conventional multiplexer. FIG. 3 is a waveform diagram showing a malfunction of a multiplexer in FIG. 1.2... D type flip-flop, 3... selection circuit, 4... delay circuit, 5, 6... signal input terminal,
7... Clock input terminal, 8... Output terminal. Patent applicant: Nippon Telegraph and Telephone Corporation Agent: Masaki Yamakawa (and 1 other person) Figure 1 Figure 4 Figure 2 (9) Plays ↑

Claims (2)

[Claims] (1) The first D-type flip-flop consists of two latches, a master and a slave, and one more latch is added after the master and slave, and the clock signal input terminal is connected to the first D-type flip-flop. A second D-type flip-flop commonly connected to that of the D-type flip-flop, two data signal input terminals to which the output terminals of the first and second D-type flip-flops are connected, and one selection signal. a selection circuit having an input terminal and selecting and outputting one of the signals input to the two data signal input terminals depending on the level of the selection signal; and an intervening circuit between the clock signal input terminal and the selection signal input terminal. A multiplexer consisting of an inserted delay circuit for timing adjustment. (2) The multiplexer according to claim 1, further comprising a third D-type flip-flop consisting of two latches, a master and a slave, whose data signal input terminal is connected to the output of the selection circuit.