JPH05102861A - Multiplexer - Google Patents

Abstract

PURPOSE:To output signals from an output terminal without generating an unstable state or malfunction by enlarging the timing margin of a select signal to a data signal. CONSTITUTION:Select signals Se1, Se2 and Se3 generated at a ring counter 25 by a clock signal CLK are inputted to a selection circuit 24 and inputted to clock signal input terminals C1, C2 and C3 at DFF 21-23 as well and at the respective DFF, the data signals are outputted to the selecting circuit 24 with the rise of the inputted select signals. When the inputted select signals Se1, Se2 and Se3 are at an 'H' level, the selection circuit 24 selects the correspondent data signals and successively outputs those signals from an output terminal 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexer for parallel-serial conversion of parallel signals input from a plurality of channels into serial signals, and more particularly to a multiplexer having a circuit configuration suitable for high speed operation.

[0002]

2. Description of the Related Art
This will be described with reference to FIGS. FIG. 6 shows a logical configuration example of a conventional multiplexer when the number of input channels is three.

In the figure, 1, 2, 3 are D-type flip-flops (hereinafter referred to as DFF) composed of two latches of a master and a slave, and 4 is a data signal input terminal D.
1, D2, D3 and selection signal input terminals S1, S2, S3. When the selection signal Se1 input to S1 is at "H" level, the data signal input to D1 is the selection signal input to S2. The data signal input to D2 when Se2 is "H", and the selection signal Se3 input to S3 is "H".
A selection circuit (SELECTO) that selects the data signal input to D3 when it is at the level and outputs it from Q4
R) and 5 are for dividing the clock signal CLK input from the clock signal input terminal 10 into a frequency of 1/3 and outputting 1
A frequency divider circuit (1/3 DIVIDER), 6 frequency-divides the input clock signal CLK into a frequency of 1/3, and phase "H" level to three output terminals (S1 ', S2', S3 '). It is a ring counter that shifts and outputs.

The data signals Ai, Bi, Ci (i = 1, 2, 3, ...) Input from the signal input terminals 7, 8, 9 are converted into 1 /
At the rising edge of the output signal DIV of the divide-by-3 circuit 5, each DF
L1, FFF2, DFF3 latch each output terminal Q
Output from 1, Q2, Q3. These output signals correspond to the signals input to the data signal input terminals D1, D2, D3 according to the signal levels of the selection signals Se1, Se2, Se3 input to the selection signal input terminals S1, S2, S3 of the selection circuit 4, respectively. One of them is selected and the serial signal of the data signals Ai, Bi, Ci is output from the output terminal Q4 of the selection circuit 4 to the output terminal 11.

FIG. 7 is a signal waveform of each part showing the operation in this logical configuration. However, the delay time in each circuit is ignored.

In the figure, DFF1, DFF2, DF
DFF1, DFF2, D are generated by the 1/3 frequency-divided signal DIV ((b) in the figure) input to the clock input terminal C of F3.
From the respective output terminals Q1, Q2, Q3 of the FF3, the signal trains Ai, Bi, Ci ((c), (d), (e) in the figure) are outputted, and these are inputted to the data signal input terminal D of the selection circuit 4.
Input to 1, D2, D3. The selection signals Se1, Se2, Se3 output from the ring counter 6 ((f) in the figure,
(G) and (h) are selection signal input terminals S1 and S1 of the selection circuit 4, respectively.
The data signal input to S1 is input to S2 and S3, and the data signal input to D1 when the selection signal Se1 input to S1 is "H" level is input to D2 when the selection signal Se2 input to S2 is "H". When the selection signal Se3 input to S3 is at the "H" level, the data signal input to D3 is selected, and the data signal to be input to the terminal D as shown in (i) in the figure.
1, data signals Ai, Bi, Ci input to D2, D3
Are sequentially output from the output terminal 11.

[0007]

As described above,
By using the configuration shown in FIG. 6, three parallel signals can be converted into one serial signal. However, the above explanation is an ideal case and is different in reality. That is, DFF
The delay times of 1, DFF2 and DFF3 are not equal. Even if these are equal and a delay circuit for compensating the delay time of DFF1, DFF2, DFF3 is provided between the selection circuit 4 and the ring counter 6 to adjust the delay time, it is not possible to completely adjust the timing. It is possible. further,
Signals have finite rise and fall times, which are generally not equal. Therefore, times Ta1, Tb1, Tc1, Ts1, and Ts indicated by arrows in FIG.
3 cannot be matched exactly. Therefore, the signal of the portion indicated by the arrow of the output signal of the selection circuit 4 (the output signal shown in (i) in the figure) becomes very unstable, and there is a big problem that a malfunction occurs.

FIG. 8 shows a specific example of this malfunction. This is because the data signals Ai, Bi and Ci are selection signals Se.
1, the case of being behind with respect to Se2 and Se3 is shown. In this case, an erroneous operation (commonly known as whiskers) occurs at the arrow portion as shown in FIG.

In order to solve this problem, conventionally, the serial data signal of (i) of FIG. 7 is input to the DFF again, the data signal is latched at the rising edge of the clock signal (FIG. 7 (a)), and the I was doing corrections and waveform shaping. However, in this configuration, the time during which the data does not change before the clock signal rises in the DFF (when the data is Ai)
And the time during which the data does not change after the clock signal rises (when the data is Ci) becomes shorter.
The phase margin of the FF has become small, making it difficult to increase the speed.

An object of the present invention is to realize a multiplexer capable of high-speed operation by eliminating a malfunction caused by an unstable operation of a conventional circuit.

[0011]

In order to achieve the above object, the present invention has a configuration in which the clock signal of the parallel data input section DFF and the selection signal for the selection circuit are shared.

[0012]

With the above configuration, each DFF inputs the selection signal generated by the clock signal and outputs each data signal to the selection circuit at the rising edge of the input selection signal, for example. On the other hand, the selection circuit selects the data signal input from the corresponding DFF when the input selection signal is, for example, “H” level, and sequentially outputs the data signals from the plurality of DFFs from the output terminal. As a result, as will be described in detail later, in the selection circuit, the timing margin of the selection signal with respect to the data signal becomes very large, and the signal can be output from the output terminal without causing an unstable state or malfunction.

[0013]

FIG. 1 shows the configuration of a first embodiment of a multiplexer according to the present invention. In the figure, reference numerals 21, 22, 23 are DFFs, 24 is a selection circuit, and 25 is a ring counter. Output terminals S1 ', S2', S of the ring counter 25
3'denotes selection signal input terminals S1 and S of the selection circuit 24, respectively.
2 and S3, the output terminal S1 'of the ring counter 25 is connected to the clock terminal C2 of the DFF 22, the output terminal S2' is connected to the clock terminal C3 of the DFF 23, and the output terminal S3 'is connected to the clock terminal C1 of the DFF 21. Has been done.

FIG. 2 shows the operation waveform of each part in this embodiment. However, the delay time of each circuit is ignored.

In FIG. 1, the DFF 22 outputs the signal Bi at the rising edge of the selection signal Se1 generated by the clock signal CLK input from the clock signal input terminal 29, the DFF 23 outputs the signal Ci at the rising edge of the selection signal Se2, and the rising edge of the selection signal Se3. Then, the DFF 21 outputs the signal Ai. The signals Ai, Bi, Ci are input to the data signal input terminals D1, D2, D3 of the selection circuit 24, respectively, and the signal Ai input to D1 when the selection signal Se1 is at "H" level.
When the selection signal Se2 is "H" level, the signal Bi input to D2 is input, and when the selection signal Se3 is "H" level, D
Select the signal Ci input to 3 and select the terminals D1, D2, D
The data signals Ai, Bi, and Ci input to 3 are sequentially output from the output terminal 30. What is particularly important here is that the period during which the selection signals Se1, Se2, Se3 are at "H" level is in the center of the data signals Ai, Bi, C, and the timing margin in the selection circuit is very large. That's what it means. Therefore, it is possible to obtain the output signal (h) without an unstable state or malfunction. Also, the fact that no delay circuit for timing adjustment is required is
This is a great advantage over conventional circuits.

Further, as in the conventional case, D is placed next to the selection circuit 24.
Even if the FF is provided to perform retiming, the timing margin (phase margin) between the clock signal and the data signal
Has a great effect that stable high-speed circuit operation can be realized without being reduced in size unlike the conventional logic configuration.

Next, the second multiplexer of the present invention is used.
The configuration of this embodiment is shown in FIG. In the figure, 41, 4
Reference numerals 2 and 43 are DFFs, 44 is a selection circuit, and 45 is a ring counter. Output terminals S1 ', S of the ring counter 45
2'and S3 'are selection signal input terminals S of the selection circuit 44, respectively.
1, S2, S3, and the output terminal S1 'of the ring counter 45 is the clock terminal C1 of the DFF 41.
The output terminal S2 'is the clock terminal C2 of the DFF42.
The output terminal S3 'is connected to the clock terminal C3 of the DFF 43, respectively.

FIG. 4 shows the operation waveform of each part in this embodiment. However, the delay time of each circuit is ignored.

In FIG. 3, the DFF 41 outputs the signal Ai at the fall of the selection signal Se1 generated by the clock signal CLK input from the clock signal input terminal 49, the DFF 42 outputs the signal Bi at the fall of the selection signal Se2, and the selection signal Se3. The DFF 43 outputs the signal Ci at the trailing edge of. The signals Ai, Bi, Ci are input to the data signal input terminals D1, D2, D3 of the selection circuit 44, respectively, and the signal Ai input to D1 when the selection signal Se1 is at "H" level.
When the selection signal Se2 is "H" level, the signal Bi input to D2 is input, and when the selection signal Se3 is "H" level, D
Select the signal Ci input to 3 and select the terminals D1, D2, D
The data signals Ai, Bi, and Ci input to 3 are sequentially output from the output terminal 50. Particularly important here is the timing relationship between the data signal and the selection signal in the selection circuit. This will be described with reference to FIG. 5, for example, in the case of the data signal D1 and the selection signal S1. At the falling time t1 of the selection signal S1 ((a) in the figure), DFF4
The data signal Ai is output from 1. Here, DFF4
The delay time of 1 is tpd. In the selection circuit 44, the DF
When the selection signal S1 that drives F41 is at "H" level,
The data signal Ai input to the data signal input terminal is selected. Therefore, the selection signal surely enters the inside of the data signal by the delay time of the DFF, and it is possible to obtain an operation with a timing margin without causing an erroneous operation as well as an erroneous operation. The great advantage that no delay circuit for timing adjustment is required is the same as in the case of the first embodiment.

Further, as in the conventional case, D is placed next to the selection circuit 44.
Even if the FF is provided to perform retiming, the timing margin (phase margin) between the clock signal and the data signal
Has a great effect that stable high-speed circuit operation can be realized without being reduced in size as in the conventional logic configuration.

In the above description, the operation of the DFF is assumed to operate at the rising edge of the clock signal in the first embodiment, and the operation of the DFF is assumed to operate at the falling edge of the clock signal in the second embodiment. It is completely free to design whether to operate the DFF at the rising edge or the falling edge of the clock signal, and it is clear that the present invention is effective in any combination. Further, although it is assumed that the selection circuit selects the data input to the corresponding data signal input terminal when the selection signal is at the “H” level, the selection circuit also selects the data at the “L” level. It is valid. However, the combination of the level of the signal that operates the DFF and the level of the signal that operates the selection circuit may be accurately combined.

In the above description, the number of parallel input signals is three.
Although the case has been described, it is needless to say that it is effective even when the number of signals is larger.

[0023]

As described above, according to the present invention,
By supplying the selection signals of different phases to the plurality of DFFs in the data input section to operate, the timing margin between the data signal and the selection signal supplied from the DFF to the selection circuit increases.

That is, in the conventional multiplexer, in order to avoid the malfunction of the output signal of the selection circuit, it is indispensable to further provide the DFF after the selection circuit, but the output data of the selection circuit is unstable. Therefore, it was difficult to increase the speed.

However, according to the present invention, no timing circuit (delay circuit) is required, the timing margin of the selection circuit is large as described above, and an output signal without malfunction can be easily obtained from the selection circuit. It has the effect that

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of a multiplexer according to the present invention.

FIG. 2 is an operation waveform diagram in the first embodiment.

FIG. 3 is a configuration diagram of a second embodiment of a multiplexer according to the present invention.

FIG. 4 is an operation waveform diagram in the second embodiment.

FIG. 5 is an operation waveform diagram in the second embodiment.

FIG. 6 is a diagram showing a configuration example of a conventional multiplexer.

FIG. 7 is an operation waveform diagram in the above conventional configuration example.

FIG. 8 is an operation waveform diagram in the above conventional configuration example.

[Explanation of symbols]

21, 22, 23 ... D type flip-flop (DF
F) 24 ... Selection circuit 25 ... Ring counter 26, 27, 28 ... Signal input terminal 29 ... Clock signal input terminal 30 ... Output terminal 41, 42, 43 ... D type flip-flop (DF)
F) 44 ... Selection circuit 45 ... Ring counter 46, 47, 48 ... Signal input terminal 49 ... Clock signal input terminal 50 ... Output terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoshi Yamaguchi 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (3)

[Claims] 1. An n (n is an integer of 3 or more) D type flip-flop DFF1, DFF2, ... DFFn and n having n output terminals (S1 ', S2', ... Sn ').
It has a ring counter of stages, n data input terminals (D1, D2, ... Dn) and n selection signal input terminals (S1, S2, ... Sn), and is input to the data input terminals according to the level of the selection signal. In the multiplexer composed of a selection circuit for selecting a data signal to be parallel-serial-converted from n parallel signal trains into one serial signal train, the output terminals S1 ′, S2 ′, ... Selection signal input terminals S1, S2, ... S of the selection circuit
n, and the output terminals of DFF1, DFF2, ..., DFFn are connected to the data input terminals D1, D2, ..., Dn of the selection circuit, and the output terminals of the ring counter are respectively clock signal input terminals of the D type flip-flop. A multiplexer characterized by being connected to. 2. The multiplexer according to claim 1, wherein output terminals S1 ', S2' ..., S of said ring counter are provided.
(N-1) 'and Sn' are defined as DFF2 and DFF, respectively.
3, ... A multiplexer characterized by being connected to clock signal input terminals of DFFn and DFF1. 3. The multiplexer according to claim 1, wherein output terminals S1 ', S2' ... Sn 'of said ring counter.
Are connected to the clock signal input terminals of the DFF1, DFF2, ... DFFn, respectively.