JPH0258452A - Loop back test system - Google Patents

Loop back test system

Info

Publication number
JPH0258452A
JPH0258452A JP63208016A JP20801688A JPH0258452A JP H0258452 A JPH0258452 A JP H0258452A JP 63208016 A JP63208016 A JP 63208016A JP 20801688 A JP20801688 A JP 20801688A JP H0258452 A JPH0258452 A JP H0258452A
Authority
JP
Japan
Prior art keywords
data string
test data
circuit
loop back
tester
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63208016A
Other languages
Japanese (ja)
Other versions
JPH0687566B2 (en
Inventor
Seiichi Yamamoto
山本 成一
Tsunetoshi Mizusawa
水沢 常利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP63208016A priority Critical patent/JPH0687566B2/en
Publication of JPH0258452A publication Critical patent/JPH0258452A/en
Publication of JPH0687566B2 publication Critical patent/JPH0687566B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Dc Digital Transmission (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To decide a fault section with one test by inserting the decision result of an error detected with a device to a position allocated with the device among a loop back test data string simultaneously when the loop back is executed on each stage. CONSTITUTION:The loop back test data column generated in a tester is inputted from an IN 1, outputted from an OUT 2 to a next stage device side, a loop back condition control is detected by a detecting circuit 11, and it is controlled to the loop back condition. At such a time, the input test data string from the tester side is compared and collated with the input test data string looped back from the next stage device inputted from the IN 2 by a comparing circuit 12, and the presence and absence of the error is outputted. Simultaneously, the test data string from the tester side is selected by a selector circuit 13 looped back to the tester side, the decision result output of the presence and absence of the error in the comparing circuit 12 is inserted to the position allocated to the device among the test data string by an inserting circuit 14, and outputted to the tester side from the OUT 1. Thus, the fault section can be decided by a single test.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多段中継伝送における折返し試験方式に関し、
特に試験データ列中の当該装置に割りふられた位置に判
定結果を挿入するととKより、1回の試行で障害区間の
判定を可能とする折返し試験方式に関するものである。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a loopback test method in multi-stage relay transmission.
In particular, the present invention relates to a loopback test method that makes it possible to determine a faulty section in one trial by inserting a determination result into a position assigned to the device in the test data string.

〔従来の技術〕[Conventional technology]

従来、多段中継の折返し試験に際しては、各段に固有の
折返しパターン列により折返し試験を実行しているのが
一般的である。
Conventionally, when performing a loopback test on a multi-stage relay, it is common to perform the loopback test using a loopback pattern sequence unique to each stage.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、上述した従来の折返し試験方式では、障害区間
を判定する九めには中継段の回数、各々試験パターンを
準備して行なわなければならないという問題があつ九。
However, the above-mentioned conventional loopback test method has a problem in that, in order to determine a faulty section, a test pattern must be prepared for each relay stage and the number of relay stages.

〔課題を解決するための手段〕[Means to solve the problem]

このような問題点を解決するため、本発明の折返し試験
方式は、被折返し試験制御を検出し、折返し状態に制御
する検出回路と、試験器側からの入力試験データ列と次
段装置側から折返ってきた入力試験データ列とを比較照
合して誤まりの有無を判定する比較回路と、折返し状態
でたい場合には次段装置側からのデータ列を選択してい
るが、折返し状態では試験器側からのデータ列を選択し
て折返す選択回路と、前記比較回路におけるエラーの有
無の判定結果を試験データ列中の当該装置に割りふられ
た位置に挿入する挿入回路とを有することを特徴とする
ものである。
In order to solve such problems, the foldback test method of the present invention includes a detection circuit that detects the loopback test control and controls it to the loopback state, and a detection circuit that detects the loopback test control and controls it to the loopback state, and a test data string input from the tester side and the input test data string from the next stage equipment side. There is a comparison circuit that compares and verifies the returned input test data string to determine whether there is an error, and if you want to be in a looped-back state, the data string from the next stage device is selected, but in the looped-back state, It has a selection circuit that selects and folds back the data string from the tester side, and an insertion circuit that inserts the determination result of the presence or absence of an error in the comparison circuit into the position allocated to the test data string in the test data string. It is characterized by:

〔作用〕[Effect]

し九がって、本発明によれば、試験データ列中の当該装
置に割りふられた位置に判定結果を挿入することにより
、1回の試行で障害区間の判定が可能になる。
Therefore, according to the present invention, by inserting the determination result into the position assigned to the device in question in the test data string, it becomes possible to determine the fault section in one trial.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

図面は本発明による折返し試験方式の一実施例を示すブ
ロック図である。同図において、INI。
The drawing is a block diagram showing an embodiment of the folding test method according to the present invention. In the same figure, INI.

0UTIはそれぞれ試験器側の入出力、IN2゜0UT
2はそれぞれ次段装置側の入出力である。
0UTI is the input/output on the tester side, IN2゜0UT
2 is the input/output of the next-stage device, respectively.

また、11は被折返し試験制御を検出して折返し状態に
制御する検出回路、12は試験器側からの入力試験デー
タ列と次段装置側から折返ってきた入力試験データ列と
を比較照合して誤まりの有無を判定する比較回路、13
は折返し状態でない場合には次段装置側からのデータ列
を選択しているが、折返し状態では試験器側からのデー
タ列を選択して折返す選択回路、14は前記比較回路1
2におけるエラーの有無の判定結果を試験データ列中の
当該装置に割りふられた位置に挿入する挿入回路である
Further, 11 is a detection circuit that detects the loopback test control and controls the loopback state, and 12 is a detection circuit that compares and collates the input test data string from the tester side and the input test data string that has been looped back from the next stage device side. a comparison circuit for determining the presence or absence of an error; 13;
14 is a selection circuit which selects the data string from the next stage equipment side when it is not in the looping state, but selects and loops the data string from the tester side when it is in the looping state; 14 is the comparison circuit 1;
This is an insertion circuit that inserts the determination result of the presence or absence of an error in step 2 into the position assigned to the device in question in the test data string.

次に、上記実施例の動作について説明する。試験器にて
発生した折返し試験データ列をINIから入力し、次段
装置側へOUT 2から出力すると共に、検出回路11
にて被折返し制御を検出し、折返し状態に制御する。こ
のとき、比較回路12で試験器側からの入力試験データ
列とIN2から入力し九次段装置側から折返ってきた入
力試験データ列を比較照合して誤まりの有無を出力する
。同時に、選択回路3で試験器側からの試験データ列を
選択して試験器側に折返す。さらに、挿入回路4でこの
試験データ列中の当該装置に割りふられた位置に前記比
較回路2におけるエラーの有無の判定結果出力を挿入し
、試験器側に0UTIより出力する。
Next, the operation of the above embodiment will be explained. The return test data string generated by the tester is input from INI and output from OUT 2 to the next stage equipment side, and the detection circuit 11
Detects loopback control and controls the loopback state. At this time, the comparison circuit 12 compares the input test data string from the tester side with the input test data string input from IN2 and returned from the ninth stage device side, and outputs the presence or absence of an error. At the same time, the selection circuit 3 selects the test data string from the tester and returns it to the tester. Furthermore, the insertion circuit 4 inserts the output of the determination result of the presence or absence of an error in the comparison circuit 2 into the position assigned to the device in this test data string, and outputs it to the tester side from 0UTI.

なお、次段装置においても同様の動作を行なう。Note that similar operations are performed in the next-stage device as well.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、各段において折返しを実
行すると同時に、折返した試験データ列中の当該装置に
割りふられた位置に当該装置にて検出したエラーの有無
の判定結果を挿入することにより、1回の試行で障害区
間の判定を行なうことができる効果がある。
As explained above, the present invention executes loopback at each stage, and at the same time inserts the determination result of the presence or absence of an error detected by the device into the position assigned to the device in the looped test data string. This has the effect of making it possible to determine the faulty section in one trial.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の一実施例を示すブロック図である。 11・・・・検出回路、12・・・・比較回路、13・
・・・選択回路、14・・・・挿入回路。
The drawing is a block diagram showing one embodiment of the present invention. 11...detection circuit, 12...comparison circuit, 13...
...Selection circuit, 14...Insertion circuit.

Claims (1)

【特許請求の範囲】[Claims] 被折返し試験制御を検出し、折返し状態に制御する検出
回路と、試験器側からの入力試験データ列と次段装置側
から折返つてきた入力試験データ列とを比較照合して誤
まりの有無を判定する比較回路と、折返し状態でない場
合には次段装置側からのデータ列を選択しているが、折
返し状態では試験器側からのデータ列を選択して折返す
選択回路と、前記比較回路におけるエラーの有無の判定
結果を試験データ列中の当該装置に割りふられた位置に
挿入する挿入回路とを有することを特徴とする折返し試
験方式。
A detection circuit that detects loopback test control and controls the loopback state compares the input test data string from the tester side with the input test data string looped back from the next stage equipment side to check for errors. A comparison circuit that makes the determination, a selection circuit that selects the data string from the next stage equipment side when it is not in the looping state, and a selection circuit that selects and loops back the data string from the tester side when it is in the looping state, and the comparison circuit. 1. An insertion circuit for inserting a determination result of the presence or absence of an error in a test data string at a position allocated to the device concerned.
JP63208016A 1988-08-24 1988-08-24 Loopback test method Expired - Lifetime JPH0687566B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63208016A JPH0687566B2 (en) 1988-08-24 1988-08-24 Loopback test method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63208016A JPH0687566B2 (en) 1988-08-24 1988-08-24 Loopback test method

Publications (2)

Publication Number Publication Date
JPH0258452A true JPH0258452A (en) 1990-02-27
JPH0687566B2 JPH0687566B2 (en) 1994-11-02

Family

ID=16549281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63208016A Expired - Lifetime JPH0687566B2 (en) 1988-08-24 1988-08-24 Loopback test method

Country Status (1)

Country Link
JP (1) JPH0687566B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6443924B1 (en) 1994-05-13 2002-09-03 Scimed Life Systems, Inc. Apparatus for performing diagnostic and therapeutic modalities in the biliary tree
US6579300B2 (en) 2001-01-18 2003-06-17 Scimed Life Systems, Inc. Steerable sphincterotome and methods for cannulation, papillotomy and sphincterotomy
US7645254B2 (en) 1994-05-13 2010-01-12 Boston Scientific Scimed, Inc. Apparatus for performing diagnostic and therapeutic modalities in the biliary tree

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6139735A (en) * 1984-07-31 1986-02-25 Nec Corp Normal supervisory system
JPS62291228A (en) * 1986-06-11 1987-12-18 Nec Corp Loopback test control circuit of transmission line

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6139735A (en) * 1984-07-31 1986-02-25 Nec Corp Normal supervisory system
JPS62291228A (en) * 1986-06-11 1987-12-18 Nec Corp Loopback test control circuit of transmission line

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6443924B1 (en) 1994-05-13 2002-09-03 Scimed Life Systems, Inc. Apparatus for performing diagnostic and therapeutic modalities in the biliary tree
US7645254B2 (en) 1994-05-13 2010-01-12 Boston Scientific Scimed, Inc. Apparatus for performing diagnostic and therapeutic modalities in the biliary tree
US6579300B2 (en) 2001-01-18 2003-06-17 Scimed Life Systems, Inc. Steerable sphincterotome and methods for cannulation, papillotomy and sphincterotomy
US7947056B2 (en) 2001-01-18 2011-05-24 Boston Scientific Scimed, Inc. Steerable sphincterotome and methods for cannulation, papillotomy and sphincterotomy

Also Published As

Publication number Publication date
JPH0687566B2 (en) 1994-11-02

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