JPH0257616U - - Google Patents

Info

Publication number
JPH0257616U
JPH0257616U JP13635388U JP13635388U JPH0257616U JP H0257616 U JPH0257616 U JP H0257616U JP 13635388 U JP13635388 U JP 13635388U JP 13635388 U JP13635388 U JP 13635388U JP H0257616 U JPH0257616 U JP H0257616U
Authority
JP
Japan
Prior art keywords
operational amplifier
circuit
output
buffer
buffer circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13635388U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0635542Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13635388U priority Critical patent/JPH0635542Y2/ja
Publication of JPH0257616U publication Critical patent/JPH0257616U/ja
Application granted granted Critical
Publication of JPH0635542Y2 publication Critical patent/JPH0635542Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)
JP13635388U 1988-10-18 1988-10-18 演算増幅回路 Expired - Lifetime JPH0635542Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13635388U JPH0635542Y2 (ja) 1988-10-18 1988-10-18 演算増幅回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13635388U JPH0635542Y2 (ja) 1988-10-18 1988-10-18 演算増幅回路

Publications (2)

Publication Number Publication Date
JPH0257616U true JPH0257616U (US06815460-20041109-C00097.png) 1990-04-25
JPH0635542Y2 JPH0635542Y2 (ja) 1994-09-14

Family

ID=31396785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13635388U Expired - Lifetime JPH0635542Y2 (ja) 1988-10-18 1988-10-18 演算増幅回路

Country Status (1)

Country Link
JP (1) JPH0635542Y2 (US06815460-20041109-C00097.png)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11298270A (ja) * 1998-04-15 1999-10-29 Nec Corp Pga(プログラマブル・ゲインアンプ)回路
WO2014038138A1 (ja) * 2012-09-07 2014-03-13 旭化成エレクトロニクス株式会社 サンプルホールド回路、a/d変換器、サンプルホールド回路のキャリブレーション方法および回路

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11298270A (ja) * 1998-04-15 1999-10-29 Nec Corp Pga(プログラマブル・ゲインアンプ)回路
WO2014038138A1 (ja) * 2012-09-07 2014-03-13 旭化成エレクトロニクス株式会社 サンプルホールド回路、a/d変換器、サンプルホールド回路のキャリブレーション方法および回路
JP5926388B2 (ja) * 2012-09-07 2016-05-25 旭化成エレクトロニクス株式会社 サンプルホールド回路、a/d変換器およびサンプルホールド回路のキャリブレーション方法
US9374104B2 (en) 2012-09-07 2016-06-21 Asahi Kasei Microdevices Corporation Sample hold circuit, A/D converter, calibration method of the sample hold circuit, and circuit

Also Published As

Publication number Publication date
JPH0635542Y2 (ja) 1994-09-14

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