JPH0256948A - Measurement of electrostatic energy - Google Patents

Measurement of electrostatic energy

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Publication number
JPH0256948A
JPH0256948A JP20686488A JP20686488A JPH0256948A JP H0256948 A JPH0256948 A JP H0256948A JP 20686488 A JP20686488 A JP 20686488A JP 20686488 A JP20686488 A JP 20686488A JP H0256948 A JPH0256948 A JP H0256948A
Authority
JP
Japan
Prior art keywords
electrostatic energy
withstand voltage
diodes
diode
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20686488A
Other languages
Japanese (ja)
Inventor
Masahito Kashima
鹿島 雅人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP20686488A priority Critical patent/JPH0256948A/en
Publication of JPH0256948A publication Critical patent/JPH0256948A/en
Pending legal-status Critical Current

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  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To measure the potential of applied electrostatic energy at an arbitrary time by previously finding the correlation of electrostatic energy with each diode in which a plurality of diodes are formed on a semiconductor board to previously deteriorate. CONSTITUTION:Six junction diodes 21-26 are formed on an N-type silicon substrate 1 to have pads 3 at both the ends thereof respectively. Since the deterioration of withstand voltage occurs in the concentration of current, the correlation between surge withstand voltage for deteriorating the withstand voltage and N-layer 6 area occurs in the diodes 21-26. Such a semiconductor substrate 1 is assembled to carry together, the withstand voltage of the diodes 21-26 is measured to detect the withstand voltage of which diode is deteriorated. Therefore, we can know till which time point and how many potentials of electrostatic energy are applied. Thereby, when a semiconductor device is assembled and carried, we can measure how many potential of the electrostatic energy are applied without the use of a practical element of a semiconductor device.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、MO3素子を含むような半導体装置に、例え
ば組立工程や運搬時などに印加される静電エネルギーの
計測方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for measuring electrostatic energy applied to a semiconductor device including an MO3 element, for example, during an assembly process or during transportation.

〔従来の技術〕[Conventional technology]

半導体装置においては、静電エネルギーによって破壊が
起こることがある。特にMO3素子においては静電エネ
ルギーによるゲート絶縁膜の破壊が起こりやすい、その
ため入力保護回路を用いて静電破壊防止対策を行ってい
るが、大きな静電エネルギーにより入力保護回路自体も
破壊される場合がある。
In semiconductor devices, destruction may occur due to electrostatic energy. Particularly in MO3 devices, the gate insulating film is easily destroyed by electrostatic energy.Therefore, an input protection circuit is used to prevent electrostatic damage, but the input protection circuit itself may be destroyed by large electrostatic energy. There is.

さらに、MO3素子に静電エネルギーが印加されるのは
組立工程中あるいは運搬時などが考えられるので人力保
護回路により静電破壊を完全に防止することは難しい、
従って、MO3素子の組立および運搬におけるどの工程
でどの程度の大きさの静電エネルギーがMO3素子に印
加されるかを計測して品質管理をすることが必要である
Furthermore, since electrostatic energy is likely to be applied to the MO3 element during the assembly process or during transportation, it is difficult to completely prevent electrostatic damage using a human protection circuit.
Therefore, it is necessary to perform quality control by measuring how much electrostatic energy is applied to the MO3 element in which step in the assembly and transportation of the MO3 element.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

半導体装置のパッケージなどに帯電した静電気量を計測
することは従来でも可能であった。しかし、静電エネル
ギーがMO3素子に印加される男系は一瞬のうちに発生
する現象であるため、実際のMO3素子にてその大きさ
を計測するのは困難であった。また組立工程および運搬
下にあるMOS素子と等しい条件で静電エネルギーの大
きさを計測するのも困難であった。
Conventionally, it has been possible to measure the amount of static electricity charged on semiconductor device packages and the like. However, since the phenomenon in which electrostatic energy is applied to the MO3 element occurs instantaneously, it has been difficult to measure its magnitude using an actual MO3 element. Furthermore, it is difficult to measure the amount of electrostatic energy under the same conditions as the MOS elements during assembly and transportation.

本発明の!IBは、半導体装置の組立および運搬などの
際にどの程度の大きさの静電エネルギーが印加されたか
を半導体装置の実用素子を用いることなく計測すること
ができる静電エネルギーの計測方法に関する。
The invention! IB relates to an electrostatic energy measurement method that can measure how much electrostatic energy is applied during assembly and transportation of a semiconductor device, without using practical elements of the semiconductor device.

〔課題を解決するための手段〕[Means to solve the problem]

上記の課題の解決のために、本発明の方法はそれぞれ一
導電形の半導体層と他導電形の半導体層の間のPN接合
の面積を変えるか、少なくとも一方の層の不純物濃度を
変えることによって異なる大きさの静電エネルギーの印
加により始めて耐圧が劣化するPN接合ダイオードを複
数形成し、所定の時点で各ダイオードの耐圧を測定して
耐圧の劣化したダイオードを検知し、ダイオードの耐圧
劣化と印加静電エネルギーとの相関関係を利用すること
により静電エネルギーを計測するものである。
In order to solve the above problems, the method of the present invention is achieved by changing the area of the PN junction between the semiconductor layer of one conductivity type and the semiconductor layer of the other conductivity type, or by changing the impurity concentration of at least one layer. A plurality of PN junction diodes whose withstand voltage deteriorates only when electrostatic energy of different magnitudes is applied are formed, and the withstand voltage of each diode is measured at a predetermined time to detect a diode whose withstand voltage has deteriorated. Electrostatic energy is measured by utilizing the correlation with electrostatic energy.

〔作用〕[Effect]

異なる導電形の半導体層によって形成されるPN接合ダ
イオードにおいては、静電エネルギーの印加による電流
の集中により接合破壊が起こり、耐圧が劣化するか短絡
状態になる。従って、PN接合面積を変えて接合面積に
比例して大きくなる印加静電エネルギーを変えるか、あ
るいは少なくとも一方の層の不純物濃度を変化させて許
容静電エネルギー量を変えれば、所定の大きさの静電エ
ネルギーの印加によって始めて耐圧が劣化するPN接合
ダイオードを得ることができる。そこで、異なる大きさ
の静電エネルギーの印加により始めて耐圧の劣化するP
N接合ダイオードを複数形成しておけば、ある時点でど
のダイオードの耐圧が劣化したかを検知することにより
、その時点までの組立工程あるいは運搬時に印加された
静電エネルギーの大きさを知ることができる。
In a PN junction diode formed by semiconductor layers of different conductivity types, junction breakdown occurs due to concentration of current due to the application of electrostatic energy, and the breakdown voltage deteriorates or a short circuit occurs. Therefore, by changing the PN junction area to change the applied electrostatic energy, which increases in proportion to the junction area, or by changing the impurity concentration of at least one layer to change the allowable electrostatic energy amount, a predetermined amount of electrostatic energy can be achieved. A PN junction diode whose breakdown voltage deteriorates only when electrostatic energy is applied can be obtained. Therefore, P
If multiple N-junction diodes are formed, by detecting which diode's breakdown voltage has deteriorated at a certain point, it is possible to know the amount of electrostatic energy applied during the assembly process or transportation up to that point. can.

〔実施例〕〔Example〕

第1図は本発明の一実施例に用いる静電エネルギー検出
素子の平面図を概念的に示し、N形シリコン基板lに6
個のPN接合ダイオード21.22,23゜24.25
.26が形成されそれぞれ両端にバッド3を有する。第
2図(al、(b)はこれらのダイオードをそれぞれ平
面透視図および断面図で示したもので、N形シリコン基
板1に低不純物濃度のP形層2を拡散にて形成し、酸化
膜4で被覆したものである。
FIG. 1 conceptually shows a plan view of an electrostatic energy detecting element used in an embodiment of the present invention.
PN junction diodes 21.22, 23°24.25
.. 26 are formed, each having a pad 3 at both ends. Figures 2 (al) and (b) show these diodes in a plane perspective view and a cross-sectional view, respectively, in which a P-type layer 2 with a low impurity concentration is formed on an N-type silicon substrate 1 by diffusion, and an oxide film is formed on the N-type silicon substrate 1 by diffusion. 4.

2層2の両端付近には高不純物濃度のP形コンタクト層
5およびN形層6が酸化膜4をマスクにしての拡散によ
り形成されており、P°層5およびN゛層6酸化W!4
4の開口部でバッド3に接続されるA7電極7に接触し
ている。各PN接合断面図21〜26の2層2の不純物
濃度1面積は同一であるが、N膨拡散層6の面積は個々
に変えである。
Near both ends of the second layer 2, a P-type contact layer 5 and an N-type layer 6 with high impurity concentrations are formed by diffusion using the oxide film 4 as a mask. 4
The opening of A7 contacts the A7 electrode 7 connected to the pad 3. The impurity concentration 1 area of the two layers 2 in each of the PN junction cross-sectional views 21 to 26 is the same, but the area of the N-swelled diffusion layer 6 is different.

第3図、および第4図は、2層2の不純物濃度が5 x
lQ”/aj、 N層6の不純物濃度力2.0 XlO
目/dで、N層6の寸法を2QnX 2Q4 、3Q4
 X30nとしたときのダイオードの順方向および逆方
向の耐圧と印加サージ電圧との関係の一例を示す。
3 and 4, the impurity concentration of the second layer 2 is 5 x
lQ”/aj, impurity concentration of N layer 6 2.0 XlO
In eyes/d, the dimensions of the N layer 6 are 2QnX 2Q4, 3Q4
An example of the relationship between the forward and reverse breakdown voltages of the diode and the applied surge voltage when X30n is shown.

線31.41がN層6の寸法が2O−X20μの場合、
線32、42がN層6の寸法が30tnaX30tna
の場合である。
When line 31.41 has dimensions of N layer 6 of 2O-X20μ,
The lines 32 and 42 indicate that the dimensions of the N layer 6 are 30tnaX30tna
This is the case.

半3体基板1は一般にアースとの間に100pPの静電
容量をもつため、N層6の寸法が20nX20−のダイ
オードは400■以上または一300v以下のサージ電
圧の印加により耐圧が低下してしまい、サージ電圧を除
去しても高くならない。上述のように、この耐圧の劣化
は電流の集中で起こるので、ダイオード21〜26でも
N層6の面積と耐圧を劣化させるサージ耐圧との間に相
関関係が生じる。従ってこのような゛半導体基板1をM
O3素子と同様の組立工程で組立て、−緒に運搬して適
時各ダイオード21〜26の耐圧と測定し、どのダイオ
ードの耐圧が劣化したかを検知すれば、どの時点までに
どのような大きさの静電エネルギーが印加されたかを知
ることができる6例えば上記の実施例では、接合面積の
異なるダイオードを形成した半導体基板と実用MO5素
子と別個に作成したが、実用のMO3素子を含むIC中
にこのダイオードを組み込むことにより、直接IC自体
に静電気の加わった工程あるいは時点とその静電エネル
ギーの大きさを計測できる。
Since the half-3 board 1 generally has a capacitance of 100 pP between the ground and the ground, a diode with an N layer 6 of dimensions 20 n x 20 - will have a reduced withstand voltage when a surge voltage of 400 V or more or -300 V or less is applied. The voltage will not increase even if the surge voltage is removed. As described above, this deterioration of the withstand voltage occurs due to concentration of current, so there is a correlation between the area of the N layer 6 and the surge withstand voltage that deteriorates the withstand voltage in the diodes 21 to 26 as well. Therefore, such a ``semiconductor substrate 1'' is
It is assembled in the same assembly process as the O3 element, transported together, and the withstand voltage of each diode 21 to 26 is measured at the appropriate time to detect which diode's withstand voltage has deteriorated. For example, in the above example, a semiconductor substrate on which diodes with different junction areas were formed and a practical MO5 element were created separately, but an IC containing a practical MO3 element was fabricated separately. By incorporating this diode into the IC, it is possible to directly measure the process or point in time when static electricity is applied to the IC itself, and the magnitude of the electrostatic energy.

また、PN接合ダイオードの不純物濃度を変えると許容
静電容量が変化するので、第2図に示すようにシリコン
基FilにP−層2を拡散にて形成し、さらにその中に
N°層6を拡散にて形成する際、P−層2あるいはN゛
層6不純物濃度を変化させることにより、異なる不純物
濃度の層から構成され、接合面積の等しいダイオードを
複数形成し、不純物濃度と耐圧の劣化する際の印加サー
ジ電圧との関係を求めておけば同様に静電エネルギーを
計測することができる。
In addition, since the allowable capacitance changes when the impurity concentration of the PN junction diode is changed, a P- layer 2 is formed by diffusion in the silicon-based Fil as shown in FIG. When forming by diffusion, by changing the impurity concentration of P- layer 2 or N-layer 6, a plurality of diodes composed of layers with different impurity concentrations and the same junction area are formed, and the impurity concentration and breakdown voltage deteriorate. Electrostatic energy can be measured in the same way if the relationship with the applied surge voltage is determined in advance.

(発明の効果〕 本発明によればPN接合ダイオードの耐圧ガ静電エネル
ギー印加時の電流の集中により劣化することを利用し、
劣化させるための静電エネルギーの異なる複数のダイオ
ードを一つの半導体基板に形成して予め劣化させる静電
エネルギーと各ダイオードの相関関係を求めておくこと
によって任意の時点までの印加静電エネルギーの大きさ
を計測することができる。従って、例えばIC組立ライ
ンでのMO3素子のゲート絶縁膜の破壊の防止などに役
立てることができる。
(Effects of the Invention) According to the present invention, by utilizing the fact that the breakdown voltage of a PN junction diode deteriorates due to concentration of current when electrostatic energy is applied,
By forming multiple diodes with different electrostatic energy for deterioration on one semiconductor substrate and finding the correlation between the electrostatic energy for deterioration and each diode in advance, the magnitude of the electrostatic energy applied up to a given point can be determined. can be measured. Therefore, it can be useful, for example, to prevent damage to the gate insulating film of an MO3 element on an IC assembly line.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例に用いる静電エネルギー計測
素子の概念的平面図、第2図は第1図の素子のPN接合
ダイオード部を示し、(alが平面透視図、伽)が断面
図、第3図および第4図はそれぞれ接合面積の異なるP
N接合断面図の順方向および逆方向での耐圧と印加サー
ジ電圧との関係線図である。 IFN形シリコン基板、ZiP形低不純物濃度拡散層、
3:バンド、6:N形高不純物濃度拡散層、7:M電極
、21,22,23,24,25,26 j P N接
合フージll1(V) 第3図 ブージ敬丘(v) 141!1 手続補正書(−ji幻 1、事件の表示 2、発明の名称 特願”’i、3−zt>tgty 肴子電ニオ・レベーi+趨・rし万へ 3、補正をする者 事件との関係 住  所 名  称
FIG. 1 is a conceptual plan view of an electrostatic energy measuring element used in an embodiment of the present invention, and FIG. 2 shows a PN junction diode portion of the element in FIG. The cross-sectional views, FIGS. 3 and 4, respectively show P with different bonding areas.
FIG. 3 is a relationship diagram between the withstand voltage and the applied surge voltage in the forward and reverse directions of an N-junction cross-sectional view. IFN type silicon substrate, ZiP type low impurity concentration diffusion layer,
3: Band, 6: N-type high impurity concentration diffusion layer, 7: M electrode, 21, 22, 23, 24, 25, 26 j P N junction fuge ll1 (V) Fig. 3 Bhuj Jingyu (v) 141! 1 Procedural amendment (-ji vision 1, indication of case 2, name of invention patent application"'i, 3-zt>tgty 贴子电子/rev i+趨・rしまんへ 3, amended person's case and Related address name

Claims (1)

【特許請求の範囲】[Claims] 1)それぞれ一導電形の半導体層と他導電形の半導体層
の間のPN接合の面積を変えるか、少なくとも一方の層
の不純物濃度を変えることによって異なる大きさの静電
エネルギーの印加により始めて耐圧が劣化するPN接合
ダイオードを複数形成し、所定の時点で各ダイオードの
耐圧を測定して耐圧の劣化したダイオードを検知し、ダ
イオードの耐圧劣化と印加静電エネルギーとの相関関係
を利用することによって静電エネルギーを計測すること
を特徴とする静電エネルギーの計測方法。
1) By changing the area of the PN junction between the semiconductor layer of one conductivity type and the semiconductor layer of the other conductivity type, or by changing the impurity concentration of at least one layer, the breakdown voltage can be increased by applying different amounts of electrostatic energy. By forming multiple PN junction diodes whose breakdown voltage deteriorates, measuring the breakdown voltage of each diode at a predetermined point in time to detect diodes with degraded breakdown voltage, and utilizing the correlation between the breakdown voltage degradation of the diode and the applied electrostatic energy. A method for measuring electrostatic energy characterized by measuring electrostatic energy.
JP20686488A 1988-08-20 1988-08-20 Measurement of electrostatic energy Pending JPH0256948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20686488A JPH0256948A (en) 1988-08-20 1988-08-20 Measurement of electrostatic energy

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20686488A JPH0256948A (en) 1988-08-20 1988-08-20 Measurement of electrostatic energy

Publications (1)

Publication Number Publication Date
JPH0256948A true JPH0256948A (en) 1990-02-26

Family

ID=16530304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20686488A Pending JPH0256948A (en) 1988-08-20 1988-08-20 Measurement of electrostatic energy

Country Status (1)

Country Link
JP (1) JPH0256948A (en)

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