JPH0256446U - - Google Patents
Info
- Publication number
- JPH0256446U JPH0256446U JP13479788U JP13479788U JPH0256446U JP H0256446 U JPH0256446 U JP H0256446U JP 13479788 U JP13479788 U JP 13479788U JP 13479788 U JP13479788 U JP 13479788U JP H0256446 U JPH0256446 U JP H0256446U
- Authority
- JP
- Japan
- Prior art keywords
- package
- hole
- glass
- external lead
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011521 glass Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988134797U JPH0723961Y2 (ja) | 1988-10-14 | 1988-10-14 | 半導体素子収納用パッケージ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988134797U JPH0723961Y2 (ja) | 1988-10-14 | 1988-10-14 | 半導体素子収納用パッケージ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0256446U true JPH0256446U (de) | 1990-04-24 |
| JPH0723961Y2 JPH0723961Y2 (ja) | 1995-05-31 |
Family
ID=31393870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988134797U Expired - Fee Related JPH0723961Y2 (ja) | 1988-10-14 | 1988-10-14 | 半導体素子収納用パッケージ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0723961Y2 (de) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001024252A1 (en) * | 1999-09-28 | 2001-04-05 | Matsushita Electric Industrial Co., Ltd. | Electronic device and method of manufacture thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0224556U (de) * | 1988-07-30 | 1990-02-19 |
-
1988
- 1988-10-14 JP JP1988134797U patent/JPH0723961Y2/ja not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0224556U (de) * | 1988-07-30 | 1990-02-19 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001024252A1 (en) * | 1999-09-28 | 2001-04-05 | Matsushita Electric Industrial Co., Ltd. | Electronic device and method of manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0723961Y2 (ja) | 1995-05-31 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |