JPH0255485U - - Google Patents
Info
- Publication number
- JPH0255485U JPH0255485U JP1988134310U JP13431088U JPH0255485U JP H0255485 U JPH0255485 U JP H0255485U JP 1988134310 U JP1988134310 U JP 1988134310U JP 13431088 U JP13431088 U JP 13431088U JP H0255485 U JPH0255485 U JP H0255485U
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- terminal
- circuit
- diode
- switch circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 10
- 230000005540 biological transmission Effects 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 7
Description
第１図はこの考案の実施例の要部を一般化して
示した回路図、第２図はこの考案の第１実施例を
示す回路図、第３図は第２図のオン時のダイオー
ドＤｌの寄生インダクタンスＬ０及びコンデンサ
Ｃｌの直列回路をコンデンサＣ２に並列に接続し
て成るリアクタンス二端子回路のリアクタンス周
波数特性を示す図、第４図は第２図の実施例の伝
送損失周波数特性を示す図、第５図はこの考案の
第２実施例を示す回路図、第６図はビデオテープ
レコーダのブロツク図、第７図は従来のＲＦスイ
ツチ回路の一例を示す回路図、第８図は第７図及
び第９図のＲＦスイツチ回路の伝送損失周波数特
性を示す図、第９図は従来のＲＦスイツチ回路の
他の例を示す回路図である。
Fig. 1 is a generalized circuit diagram showing the main parts of the embodiment of this invention, Fig. 2 is a circuit diagram showing the first embodiment of this invention, and Fig. 3 is the diode D when turned on in Fig. 2. A diagram showing the reactance frequency characteristics of a two-terminal reactance circuit formed by connecting a series circuit of a parasitic inductance L0 of L0 and a capacitor C1 in parallel to a capacitor C2 . Figure 4 shows the transmission loss frequency of the embodiment of Figure 2. 5 is a circuit diagram showing the second embodiment of this invention, FIG. 6 is a block diagram of a video tape recorder, FIG. 7 is a circuit diagram showing an example of a conventional RF switch circuit, and FIG. This figure shows the transmission loss frequency characteristics of the RF switch circuits shown in FIGS. 7 and 9, and FIG. 9 is a circuit diagram showing another example of the conventional RF switch circuit.
Claims (1)
１が接続され、その第１コンデンサｃ１の入力端
及び出力端はそれぞれ第１、第２コイルｌ１，ｌ
２を通じて接地されて、π形の高域フイルタ区間
が構成され、 上記第１コンデンサｃ１の入力端及び出力端は
それぞれ制御端子に印加される制御電圧の大きさ
によつてオン、オフ制御されるスイツチ回路を通
じて接地されて成るπ形部分回路を含むＲＦスイ
ツチ回路において、 第２コンデンサｃ２及びダイオードｄの直列回
路が上記第１コンデンサｃ１と並列に接続され、
それら第２コンデンサｃ２とダイオードｄとの接
続点は抵抗器ｒを介して上記制御端子に接続され
、 オンに制御された上記ダイオードｄの寄生イン
ダクタンスｌ０及び上記第２コンデンサｃ２の直
列回路が上記第１コンデンサｃ１に並列に接続さ
れて成るリアクタンス二端子回路の反共振周波数
を上記入力端子から出力端子への伝送を阻止しよ
うとする周波数帯域の近傍に設定することを特徴
とするＲＦスイツチ回路。[Claims for utility model registration] A first capacitor c between the input terminal and the output terminal.
1 is connected, and the input terminal and output terminal of the first capacitor c 1 are connected to the first and second coils l 1 and l, respectively.
2 to ground, forming a π-shaped high-pass filter section, and the input and output terminals of the first capacitor C1 are controlled to be turned on and off depending on the magnitude of the control voltage applied to the control terminal, respectively. In an RF switch circuit including a π-type partial circuit grounded through a switch circuit, a series circuit of a second capacitor c2 and a diode d is connected in parallel with the first capacitor c1 ,
The connection point between the second capacitor c2 and the diode d is connected to the control terminal via the resistor r, and the parasitic inductance l0 of the diode d controlled to be turned on is connected to the series circuit of the second capacitor c2 . is connected in parallel to the first capacitor C1 , and the anti-resonance frequency of the two-terminal reactance circuit is set near a frequency band in which transmission from the input terminal to the output terminal is to be prevented. switch circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988134310U JPH079271Y2 (en) | 1988-10-13 | 1988-10-13 | RF switch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988134310U JPH079271Y2 (en) | 1988-10-13 | 1988-10-13 | RF switch circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0255485U true JPH0255485U (en) | 1990-04-20 |
| JPH079271Y2 JPH079271Y2 (en) | 1995-03-06 |
Family
ID=31392953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988134310U Expired - Lifetime JPH079271Y2 (en) | 1988-10-13 | 1988-10-13 | RF switch circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH079271Y2 (en) |
-
1988
- 1988-10-13 JP JP1988134310U patent/JPH079271Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH079271Y2 (en) | 1995-03-06 |
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