JPH0253784B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an image forming apparatus that forms an image on a recording medium. Conventionally, various methods have been proposed in which a latent image potential on a recording medium is detected and an apparatus is controlled using a detection signal. Processing this potential control using a digital computer is very effective in improving control stability and reliability. However, when a potential control function is added to a microcomputer for sequence control, the load on the microcomputer increases, making it impossible to perform high-speed and highly reliable processing, or degrading other functions. The present invention has been made in view of the above points, and its purpose is to enable high-speed and reliable control without degrading other functions when controlling operations using a digital computer. An object of the present invention is to provide an image forming apparatus that is capable of providing an image forming apparatus. That is, the present invention provides an image forming means comprising a plurality of process means for forming an image on a photoreceptor, a detection means for detecting the surface potential of the photoreceptor, a step of detecting the surface potential of the photoreceptor by the detection means, and and a control step for controlling the output of a specific process means among the plurality of process means based on the surface potential detected in the detection step, and the surface potential of the photoreceptor is increased by executing the program. a first digital computer that sequentially controls the image forming means, and a second digital computer that outputs a timing signal for instructing the first digital computer to detect the surface potential of the photoreceptor. a digital computer, the first digital computer initializes when a reset signal is input from the second digital computer, and further determines that the timing signal is input from the second digital computer after the initialization. Then, there is provided an image forming apparatus characterized in that the detection step and the control step are thereafter executed independently of the sequence control by the second digital computer. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1a is a sectional view of a copying apparatus to which the present invention can be applied. The surface of the drum 47 is made of a three-layer seamless photoconductor using a CdS photoconductor, is rotatably supported on a shaft, and is rotated in the direction of the arrow by a main motor 71 activated when the copy key is turned on. Start. When the drum 47 rotates by a predetermined angle, the original placed on the original platen glass 54 is moved to the first scanning mirror 44.
illuminated by an illumination lamp 46 integrally configured with
The reflected light is scanned by the first scanning mirror 44 and the second scanning mirror 53. The first scanning mirror 44 and the second scanning mirror 53 move at a speed ratio of 1/2, so that the original is scanned while the optical path length in front of the lens 52 is always kept constant. The above reflected light image shows the lens 52 and the third mirror 55.
After passing through, an image is formed on a drum 47 at an exposure section. The drum 47 is simultaneously neutralized by the pre-exposure lamp 50 and the pre-AC charger 51', and then corona-charged (for example, +) by the primary charger 51. Thereafter, the drum 47 is the exposure section, and the image irradiated by the illumination lamp 46 is slit-exposed. At the same time, AC or corona charge removal with a polarity opposite to the primary one (for example -) is performed by a charge remover 69, and then a high-contrast electrostatic latent image is formed on the drum 47 by uniform surface exposure using the entire surface exposure lamp 18. The electrostatic latent image on the photosensitive drum 47 is then liquid-developed by the developing roller 65 of the developing device 62 and visualized as a toner image, and the toner image is made easy to transfer by the pre-transfer charger 61. Upper cassette 10 or lower cassette 11
The transfer paper inside is fed into the machine by a paper feed roller 59, and is sent toward the photosensitive drum 47 with accurate timing by a register roller 60, so that the leading edge of the latent image and the leading edge of the paper are aligned at the transfer section. Can be done. Next, while the transfer paper passes between the transfer charger 42 and the drum 47, the toner image on the drum 47 is transferred onto the transfer paper. After the transfer is completed, the transfer paper is separated from the drum 47 by the separation roller 43, sent to the conveyance roller 41, guided between the hot plate 38 and press rollers 40, 41, and fixed by pressure and heat. The paper is discharged to the tray 34 by the discharge roller 37 via the paper detection roller 36 . After the transfer, the drum 47 continues to rotate, and the surface of the cleaning roller 48 is cleaned by a cleaning device comprising an elastic blade 49, and the process proceeds to the next cycle. Here, a surface electrometer 67 for measuring the surface potential is connected to the drum 47 between the entire surface exposure lamp 18 and the developing device 62.
mounted in close proximity to the surface of the As a cycle executed prior to the above copy cycle, there is a step of pouring a developer into the cleaning blade 49 while the drum 47 is stopped after the power switch is turned on. Hereinafter referred to as Priwetsu. This is to flush out the toner accumulated near the cleaning blade 49 and to provide lubrication to the contact surface between the blade 49 and the drum 47. After the prewetting time (4 seconds), the drum 47 is rotated, residual charges and memory on the drum 47 are erased using a pre-exposure lamp 50, a pre-AC static eliminator 51', etc., and the drum surface is cleaned using a cleaning roller 48 and a cleaning blade 49. There are steps. Hereinafter, this will be referred to as forward rotation. This is to make the sensitivity of the drum 47 appropriate and to form an image on a clean surface. The pre-wet time and pre-rotation time (number) are automatically changed depending on various conditions (described later). Also, as a cycle after the set number of copy cycles are completed, the drum 47 is rotated several times.
There is a step in which residual charges and memory on the drum are removed using an AC charger 69 or the like, and the drum surface is cleaned. Hereinafter referred to as post-rotation LSTR. This is to leave the drum 47 electrostatically and physically clean. As explained above, according to the present invention, the initialization and optimization control of the digital computer for optimizing image forming conditions is executed by simply outputting a plurality of timing signals from the digital computer for sequence control, resulting in high-speed processing. This makes it possible to reduce the load on the digital computer for sequence control without degrading other functions. Further, since the digital computer for optimizing the image forming conditions can be initialized and the optimizing control can be executed at an appropriate timing matching the sequence, reliability is improved. FIG. 1b is a plan view of the vicinity of the blank exposure lamp 70 in FIG. Blank exposure lamp 70-1
70-5 are turned on when the drum is rotating and not during exposure to erase surface charges and prevent excess toner from adhering to the drum. However, since the blank exposure lamp 70-1 illuminates the drum surface corresponding to the surface electrometer 67, the surface electrometer 67
When measuring the dark potential, the light is turned off momentarily. Furthermore, in B-size copying, the image area is smaller than A4 or A3 size, so the blank exposure lamp 70-5 is turned on for the non-image area even when the optical system is moving forward. The lamp 70-0 is called a sharp cut lamp, and it irradiates light onto the portion of the drum that is in contact with the separation guide plate 43-1, completely erasing the charge on that portion and preventing toner from adhering to it. I try not to contaminate the width of the separation chip. This sharp cut lamp is always lit while the drum is rotating. At each processing position in the copying process of such an electrophotographic copying device, how does the surface potential of the photosensitive drum correspond to the bright areas (areas that reflect more light) and dark areas (areas that reflect less light) of the document? Figure 2 shows how it changes. What is necessary for the final electrostatic latent image is the surface potential at point C in the figure, and the surface potentials a and b in the dark and bright areas are the surface potentials of the photosensitive drum 47.
When the ambient temperature of the photosensitive drum 47 increases, it changes as shown in Fig. 3 A' and B', and as the photosensitive drum 47 ages, it changes as shown in Fig. 4 A' and B'. Contrast cannot be obtained. A method for compensating for changes in surface potential due to temperature changes or aging will be described in detail below. First, a surface electrometer as a detection means for detecting surface potential will be explained. Figure 5 is a side sectional view of the surface electrometer, and Figure 6 is a side sectional view of the surface electrometer.
Figure 7 is a cross-sectional view taken along line X-X' in the figure and viewed from the right side of the drawing, Figure 7 is a cross-sectional view taken along line X-X' in Figure 5 and viewed from the left side of the figure, and Figure 8 is an electrometer. FIG. In Figures 5, 6, 7, and 8, the entire electrometer is
It is covered with a metal shield member 81 and a metal base 95 to eliminate the influence of external electric fields. The shield member 81 has an opening for a measurement window 88, and the measurement window 88 is opposed to the portion to be measured of the drum 47 to measure the potential. A tuning fork 82 is attached to the base 95 in an electrically conductive state, and the drive circuit shown in FIG. When voltage is applied, tuning fork 8
Self-excited vibration is performed at the mechanical resonance frequency of 2. One tip of the vibrating piece of the tuning fork constitutes a chopper electrode 83, and the vibration of the tuning fork causes the measurement window 88 to open and close at regular intervals. A printed circuit board 86 is fixed to the rear side of the chopper electrode, and a measurement electrode 85 having the same shape as the window is formed at a position facing the measurement window using a copper foil pattern on the printed circuit board. The electric lines of force based on the surface charge of the photosensitive drum 47 are:
The electric force enters the measuring electrode 85 through the measuring window 88, but the chopper electrode 83 located between the measuring window 88 and the measuring electrode interlinks and cuts the lines of electric force due to the vibration of the tuning fork 82. , an AC voltage having an amplitude proportional to the voltage difference between the surface potential on the photosensitive drum 47 and the chopper electrode (same potential as the shield member potential) is induced in the measurement electrode. The alternating current signal is passed through a current amplification circuit (15th
After being converted to a low impedance signal by
Externally taken out as the output of the electrometer. Reference numeral 89 in FIG. 8A is an internal shield member for preventing the drive signal from the tuning fork drive section 84 from being guided to the measurement electrode 85. As shown in FIG. 13, piezoelectric elements 84-1 and 84-2 are bonded to the fulcrum side of the vibrating piece of the tuning fork 82 at opposing positions in the length direction using a conductive adhesive. 84-1 and 84-2 are piezoelectric elements that generate distortion in the plane direction when an electric field is applied in the thickness direction.
When it is sandwiched between electrodes 99 and fixed with conductive adhesive 98 to the vibrating piece of the tuning fork 82 made of an elastic metal such as phosphor bronze, it forms a unimorph vibrator together with the vibrating piece, and piezoelectric Since the shape of the element is elongated in the longitudinal direction of the vibrating element, applying an electric field in the thickness direction causes distortion in the longitudinal direction of the vibrating element. The driving of the tuning fork will be described later. To attach the electrometer to the copying machine body, use the support base 95.
is fixed to a board 97, and this printed circuit board is supported by the main body by a board connector 94 and a board guide 87. On the connector insertion side of the printed circuit board 67, the connector contact terminal part is made of copper foil, and supplies power to the electrometer and takes out the output signal, making it possible to easily remove the electrometer. There is. As described above, driving the tuning fork with a piezoelectric element does not require a high-precision small motor, compared to the conventionally proposed method of intermittent electric lines of force driven by a motor, resulting in lower costs. Since the resonant frequency of the piezoelectric element is constant, highly accurate detection and device control based on the detection are possible. Next, an overview of the surface potential control method will be explained. In this embodiment, in order to detect the drum surface potential in bright and dark areas, the document illumination lamp 4 shown in FIG.
6 is not used, but a blank exposure lamp 70 is used. The surface potential of the portion of the drum surface that is irradiated with light from the blank exposure lamp 70 is measured as the bright surface potential, and the surface potential of the portion of the drum surface that is not irradiated with the light of the blank exposure lamp is measured as the dark surface potential. First, the values of the bright and dark potentials that allow obtaining an appropriate image contrast are set as target values. In this example, the target bright area potential V _L0 is −
The target dark potential V _D0 was set to 102V and +474V.
In this embodiment, since the surface potential is controlled by controlling the current flowing through the primary charger and the AC static eliminator, the bright area potential and the dark area potential are the target potentials V _L0 and V _D0 respectively.
It is assumed that the positive charger reference current DC ₁ and the AC charger reference potential AC ₁ are as follows. In this embodiment, DC ₁ =350 μA AC ₁ =160 μA. Explain the control procedure. First, the surface potential detected at the first time is determined as a bright area potential V _L1 and a dark area potential V _D1 respectively, and how much difference there is from the target bright area potential V _L0 and the target dark area potential V _D0 , respectively. The difference voltages are △V _L1 and △V _D1, respectively.
Then, △V _L1 = V _L0 −V _L1 (1) △V _D1 = V _D0 −V _D1 (2) The difference in potential in the bright area is corrected by an AC charger, and the difference in potential in the dark area is corrected by a primary charger. However, in reality, when an AC charger is controlled, not only the bright area potential but also the dark area potential is affected. Similarly, controlling the primary charger affects not only the dark potential but also the bright potential, so a modification method was adopted that takes both the AC charger and the primary charger into consideration. The corrected current value △DC ₁ of the primary charger is △DC ₁ = α ₁ △V _D1 + α ₂ △V _L1 (3). Here, the setting coefficients α ₁ and α ₂ are changes in the current value of the primary charger when the surface potentials V _D and V _L are changed, respectively, and can be expressed as follows. α ₁ = △DC (Change in primary charger current) / △V _D (Change in dark potential (4)) α ₂ = △DC (Change in primary charger current) / △V _L (Change in light potential (5) On the other hand, the corrected current value △I _Ac1 of the AC charger is: △AC=β・△V _D1 +β ₂・△V _L1 (6) Here, the setting coefficients β ₁ and β ₂ can be expressed as follows. β ₁ = △AC (change in AC charger current) / △V _D (change in dark potential) (7) β ₂ = △AC (change in AC charger current) / △V _L (change in light potential) )(8) Therefore, the positive charger current DC ₂ after the first correction
and the AC charger current _AC2 is expressed as follows. From equations (4)(5)(1), similarly, DC ₂ =α ₁・△V _D1 +α ₂・△V _L1 +DC ₁ AC ₂ =β ₁・△V _D1 +β ₂・△V _L1 +AC ₁ (9 ) (10) Here, the setting coefficients α ₁ , α ₂ , β ₁ , and β ₂ are determined based on predetermined charging conditions such as ambient temperature, humidity, and the state of the corona charger, so changes in the atmosphere,
Because it is not known whether the surface potential will reach the target value with one control due to deterioration of the charger, etc., the surface potential is measured multiple times when the device is in a specified state, and the output of the corona discharge device is controlled the same number of times as the measurements. ing. Furthermore, since the desired coefficient values of the coefficients α ₁ , α ₂ , β ₁ , and β ₂ change depending on variations in the photosensitive drum, etc., it is possible to select from four values for each coefficient. Since the second and subsequent corrections use the same method as the first correction described above, the current value DC(n+) of the positive charger and AC charger after the nth correction
1), AC(n+1) can be expressed as follows. DC(n+1)=α ₁・△V _D n+α ₂・△V _L n+DCn AC(n+1)=β ₁・△V _D n+β ₂・△V _L n+ACn Figure 9 a and b show the primary charger control current Ip It shows the change in the dark potential when the is corrected three times. 9th
Figure a shows the case where the set calibration coefficient is smaller than the actual coefficient, and Figure 9 b shows the case where the set calibration coefficient is larger than the actual coefficient. In this embodiment, the number of corrections was set as shown in the table below.

[Table] By setting in this way, it is possible to further stabilize the surface potential on the photoreceptor and at the same time to minimize the decrease in copy speed. Also, in state 1, the previous control output current value of the AC charger in the primary charger section is memorized and the primary charger and AC charger are controlled by that value, and in state 2, the previous control output current value is stored in the photosensitive area. It detects and controls the surface potential by flowing it through the body. However, in states 3 and 4, the reference current DC ₁ is applied to the photoreceptor during the first correction measurement.
Run AC ₁ . That is, in states 3 and 4, the control current used in the previous copy is reset, the reference current is returned, the surface potential is measured, and the output current is controlled.
Furthermore, if a copy operation is performed continuously for 30 minutes without leaving it for more than 30 seconds, one correction will be made after 30 minutes have passed. In this embodiment, the developing bias voltage is further controlled. FIG. 10a shows a schematic cross-sectional view for explanation. This is done in the following way. Immediately before exposing the original, a standard white plate 80 attached to the side of the original table glass 54 is irradiated with a halogen lamp 46 for exposing the original, and the scattered reflected light is sent to the drum 47 via mirrors 44, 53, 55, lens 52, etc. irradiate.
This irradiation light amount is the standard light amount, and then the lamp 81
The exposure amount when the scanner moves and actually exposes the document is changed to an exposure amount arbitrarily set by the operator.
The surface electrometer 67 measures the surface potential v _L of the portion of the drum 47 irradiated with the scattered reflected light, and sets the voltage obtained by adding +102 V to the measured value v _L as the developing bias voltage V _H. Due to the developing bias voltage V _H , the potential of the toner becomes almost the same as the bias voltage. For example, when the standard bright area potential, that is, the measured value V _L is -150V, the potential of the toner becomes -48V, and the toner and drum repel, and the toner Since it does not adhere to the surface of the document, fogging of the background portion of the document can be prevented and stable development can be performed at all times, and as a result, stable images can be obtained. In addition, in this embodiment, a standard white plate 80 corresponding to the white part of a general original is irradiated with a standard amount of light, and when the original is actually exposed, the exposure amount is changed to an arbitrary value set by the operator, so that the original back is not exposed. Even when the ground is not white but colored, a stable image can be obtained by changing the bright area surface potential of the drum depending on the exposure amount. A lighting control circuit for adjusting the amount of light from the document exposure lamp 46 is shown in FIG. 10b. In the figure, k301 is a relay in a normal state as shown in the figure, which turns off the power to the lamp _LA1 in the event of an abnormality. When the switch SW11 is turned on by a timing output IEXP signal from a DC controller (not shown), the triac Tr is activated to light the lamp. Please refer to the time chart in FIG. 11 for the timing. This device adjusts the copy density by changing the amount of light emitted from the lamp LA. For this purpose, a dimming circuit is provided to change the amount of light by controlling the phase of the amount of current supplied according to the amount of displacement of the density adjusting means VR106 using a triax. Relay K103 performs dimming operation by resistor VR106 in the state shown in the figure, and performs dimming by the same amount (standard light amount) as when lever 5 is operated in the reverse state. Switch SW1 is activated by the standard light intensity signal SEXP.
When No. 2 is turned on, the standard white plate is irradiated with the amount of light No. 5, the bright area potential (on the photoreceptor) is measured, and the bias voltage of the developing roller is determined according to that value. As described above, since the developing bias voltage _VH is determined by exposing the standard white plate 80 to light using the document exposure lamp that actually uses exposure, the precision of the control of the developing bias voltage is improved, and the control is performed just before exposing the document. There is no reduction in copy speed due to the slow speed. Furthermore, since the exposure amount is changed to an amount arbitrarily set by the operator when exposing the original, a stable image can be obtained without fogging even when the background of the original is not white but colored. FIG. 11 shows a time chart for performing the image formation and surface potential control described above. In FIG. 11, INTR is a pre-rotation for erasing the residual charge on the drum and making the drum proper, and is always executed before the copying operation.
CONTR-N is a drum rotation to keep the drum in a steady state depending on the standing time, and at the same time,
A surface potential meter measures the bright area potential V _L and dark area potential V _D alternately each time the drum rotates, and the surface potential of the drum surface is kept close to the target value by the action of a surface potential control circuit, which will be described later. Although the surface potentials V _D and V _L are detected once per rotation, it is of course possible to detect the surface potentials V D and V L multiple times. CR1 is the bright area potential V _L and the dark area potential at 0.6 rotations of the drum.
This is the drum rotation that detects _VD and controls the corona charger. CR2 is the rotation of the drum immediately before the start of copying, and is used to measure the bright area potential with a standard amount of light from the document illumination lamp and to determine the bias value for the developing roller. It is always executed when copying starts.
SCFW indicates that the optical system is moving forward. In other words, it shows the actual copy operation rotation. SCRV indicates that the optical system is moving backward. LSTR indicates backward rotation. STBY1～STBY
4 indicates the standby state of the machine. A circuit for performing the surface potential control described above will be described below. First, FIG. 12 shows a block diagram of a surface potential measuring circuit. By chopping the potential difference between the surface potential on the drum 47 and the measurement electrode 85 using the vibrator 82, the preamplifier circuit 101 amplifies the current, and the bandpass filter 102 removes noise and amplifies the current. The amplified signal is a signal synchronized with the tip signal of the vibrator, isolated by a photocoupler 104, and supplied to a clamp circuit 111. The measurement signal is determined by the synchronization signal from the synchronization circuit 108 to determine whether the potential difference between the drum 47 and the electrode 85 is positive or negative, and is clamped. A DC component of the signal is extracted by an integrating circuit 113, a high voltage is generated by a DC-DC inverter 116, and a potential is applied to the shield 81 and chopper 82 of the sensor 67. Here, if the circuit from preamplifier 101 to DC-DC inverter 116 is considered as one amplifier, it will work as an inverting amplifier. When the surface potential of the drum is smaller than the shield potential of the sensor, the potential applied to the shield 81 of the sensor is increased, and when the shield potential of the sensor 67 is higher than the drum, the potential applied to the shield 81 of the sensor is lowered. Eventually, the surface potential of the drum 47 and the shield potential of the sensor become the same. That is, the output obtained by dividing the potential of the sensor by the voltage dividing circuit 117 measures the surface potential of the drum. All circuits within 100 surrounded by broken lines are circuits that use the output voltage of the DC-DC inverter 116 as the reference voltage (earth side potential), and are all insulated from external circuits by photocouplers to prevent noise generation. There is. Each circuit shown in FIG. 12 will be explained in detail below. FIG. 13 shows a vibrator drive circuit 105, a vibrator drive switch 106, and photocouplers 107, 11.
0 shows a detailed circuit diagram of the synchronization circuit 108. When a sensor drive signal given from a potential control unit circuit to be described later is input to the terminal 120, the photocoupler 107 consisting of a light emitting diode and a phototransistor turns on the transistor Tr50, and Vcc power is supplied to the transistors Tr51 and Tr52. When the vibrator 82 vibrates, the piezoelectric element 8
A signal is output from 4-2 and supplied to the base of transistor Tr51 via capacitor C50. The signal is current-amplified by Tr51, and then passed through resistor R52 and capacitor C52 to transistor
The current is amplified by Tr52. The signal of the transistor Tr52 is transmitted to the piezoelectric element 84- via the capacitor C54.
Drive 1. As described above, the entire circuit forms an oscillation loop. The output of the transistor Tr51 is connected to an operational amplifier Q5 via a capacitor C55.
It is input to a phase shift circuit whose base is 0. The phase shift is changed by a phase shift circuit, and the signal is compared by an operational amplifier Q51 through a capacitor C57. The compared signal passes through a resistor R60 and a Zener diode ZD50, turns on and off the light emitting diode of the photocoupler 110, and outputs a synchronizing signal to the terminal 121. FIG. 14 shows the preamplifier circuit 10 of FIG.
1. Bandpass filter 102, amplifier 103,
3 is a detailed circuit diagram of the photocoupler 104. FIG. The high-impedance measurement signal induced in the measurement electrode 85 is converted into a low-impedance signal by the FET Q101, and is amplified via the capacitor C101 by a multiple feedback bandpass circuit having an operational amplifier Q102, and noise is removed.
A variable resistor VR101 adjusts the center frequency of the filter. The output of the operational amplifier Q102 is amplified by the operational amplifier Q103 via the capacitor C104, and then the light emitting diode LED101 of the photocoupler 104 is caused to emit light with a brightness according to the measurement signal. A variable resistor VR102 adjusts the amplification gain. Photocoupler phototransistor Q104
The output corresponding to the current flowing through is input to the clamp circuit. FIG. 15 shows a detailed circuit diagram of the clamp circuit 111 and the integration circuit 113 shown in FIG. 12. The output of the photocoupler 104 is applied to a terminal P119, current amplified by an emitter follower Tr104, and then connected to a capacitor C207. The opposite terminal of capacitor C207 is FET
Tr105 source follower gate and Tr10
It is connected to the drain of FET switch 6,
If the FET switch of Tr106 is cut off, Tr10
Since the gate of C207 and the drain of Tr106 have high impedance, there is no place for the charges charged in C207 to escape, so the terminal potential on the Tr gate side of C207 changes in the same way as the terminal potential on the opposite side. On the other hand, the output pulse PLS3 of the photocoupler 110
is connected to the input terminal P120 and turns on the transistor Tr107 at the timing of the negative pulse. The output of operational amplifier Q105 varies from 0 to ± by Zener diodes ZD1 and ZD2 for clamping.
Since it is limited to 5V, when Tr107 conducts, the cathode of diode D101 is biased to +12V, D101 is cut off, and the FET switch is turned off.
Zero bias is applied between the source and gate of Tr 106, and conduction is established between the drain and source of Tr 106. When Tr106 becomes conductive, operational amplifier Q
The feedback loop of 105 is the FET switch Tr106,
Since it is formed by the route of source follower Tr105 and resistor R221, the potential difference between the two input terminals of Q105 becomes zero, and considering that the input resistance of Q105 is high, the source potential of Tr105 becomes OV.
(ground potential), and the terminal voltage on the gate side of Tr105 of C207 changes from OV to the gate side of Tr105.
It comes to be biased to a potential shifted by the source-to-source voltage. When the output pulse PLS3 of the terminal P120 returns to a high level after the timing of the negative pulse ends, the transistor Tr107 is cut off and the diode D10
1 becomes conductive, current flows through the resistors R226 and R230, a deep reverse bias is applied to the gate of Tr106, and Tr106 is cut off. When Tr106 is cut off, as described above, the terminal voltage on the gate side of Tr105 of capacitor C207 shows the same change as the terminal potential on the opposite side. FIG. 17 shows a timing chart showing the operation of the clamp circuit. is a measurement signal applied to the terminal P119, a solid line indicates a case where the measurement potential is positive with respect to the chopper potential, and a broken line indicates a case where the measurement potential is negative with respect to the chopper potential. is a synchronization signal from a synchronization circuit applied to terminal P120. As shown in the output of the clamp circuit, when the measured potential is positive with respect to the chopper potential, the negative peak is OV.
A waveform having the same shape as the output of an isolator clamped to (ground potential) is obtained. Further, as shown by the broken line, when the measured potential is negative with respect to the chopper potential, a waveform having the same shape as the output of the isolator with the positive peak clamped to OV is obtained. The output is operational amplifier Q10
In the integrating circuit 113, the current is amplified by the resistor R231 and the capacitor C208, and the current is amplified by the operational amplifier Q107, and then connected to the inverter drive circuit 115. The inverter drive circuit and DC-DC inverter are shown in FIG. 16, and are composed of one DC-DC inverter and one operational amplifier. Inverter transformer T101, transistor
Inverter 1 consisting of Tr110 and Tr111
16 is a variable inverter, from 0 to
1.5KV output with capacitor C221 and resistor R24
It is designed to be taken out at both ends of the transformer T1.
The low voltage side terminal of D101 is connected to the -600V output terminal obtained from the potential control unit described later, so the cathode of D102 has -600V to +900V.
A variable output can be obtained. The output of the integrating circuit 113 is connected to an operational amplifier Q107 via a terminal P122, and after amplifying the voltage difference between it and the DC potential selected by a volume VR101 (described later), the output is connected to an inverter transformer via buffer transistors Tr108 and Tr109. Q107 is applied to the common terminal of the primary side of T101 and is
boosts the output by about 100 times. VR101 is
The DC potential applied to the negative input terminal of Q107 with the offset voltage correction volume is almost OV.
(ground potential). The output, that is, the feedback voltage V _F boosted by the transformer T101 is fed back to the chopper part 83 and the shield member 81 via the terminal P123, so that the part to be measured and the electrometer are connected to the negative voltage.
A feedback control system is configured, and the input voltage of P122 is changed so that the potential difference between the inputs of operational amplifier Q107 becomes zero, that is, the potential of chopper 83 and shield member 81 becomes equal to the voltage to be measured. The input voltage at the negative input terminal is set to zero. When the potential to be measured Vp is within the range of -600 to +900V, the output voltage of the inverter 116, that is, the feedback voltage
V _F is always equal to the potential to be measured Vp. The output of the DC-DC inverter 116 is attenuated to 1/301 by the voltage dividing circuit 117 and taken out to the output terminal P124. The detection output taken out from terminal P124 is sent to terminal TP1 shown in FIG. The feedback voltage V _F is applied to the chopper 83 and the shield member 81 and changes so that the potential difference with the potential to be measured Vp is always zero.
The output taken out in step 3 is a stable output that is not affected by the offsets and errors of each circuit from the preamplifier circuit 101 to the inverter 116. Next, the potential control unit circuit diagram shown in FIG. 18 will be explained. The CPU 1 is a microcomputer that stores programs for outputting signals to drive and control each part of the copying machine, and outputs signals such as the drum clock pulse DCK synchronized with the rotation of the drum 47, the jam detection signal JAM, and the signals from the key matrix KM. Based on the input signals, drum rotation signal DRMD, document table forward signal SCFW, reverse signal SCRV, document illumination lamp drive signal IEXD, primary charging drive signal
HVDC, AC static eliminator drive signal HVAC and indicator
Outputs output signals etc. to DPY. Along with this, a microcomputer for potential control
It outputs a signal to control the CPU2. Microcomputer CPU for sequence control
Primary charger drive signal HVDC from 1, AC static eliminator drive signal HVAC, bright area potential detection timing pulse V _L CTP, dark area potential detection timing pulse V _D
CTP, standard bright area potential detection timing pulse V _L
CTP and developer drive signal DBTP are connected to input terminals T0, T1 of potential control microcomputer CPU2 and data buses DB0 to DB3 via inverter buffers Q20 and Q21. Further, the initial reset pulse is input to the terminal of the CPU 2 via the inverter Q20-7. Based on these timing signals, the CPU 2 takes in surface potential A/D conversion data, which will be described later, performs predetermined arithmetic processing internally, and uses the results as the primary current control value, secondary current control value, and development bias control value for the D/A. Output to converter. In addition, by switching the mode changeover switch SW1, the value that causes the reference current to flow through the primary and secondary chargers regardless of the above-mentioned control value is set, and for the developing bias, the value equivalent to OV is set by the CPU.
It is also possible to output more. The surface potential measured by the surface electrometer and the potential measuring circuit shown in FIG. 12 is input to terminal TP1. Furthermore, the surface potential is connected to the operational amplifier Q via the resistor R40-4.
It is input to the inverting input terminal of 23-3, and the resistor R40
It is inverted and amplified with a gain determined by the ratio of -4 and R40-5. A resistor R4 is connected to the non-inverting input terminal of Q23-3.
5-1 and R45-2, a +6V bias is applied to perform level shifting. Q23-
The output of No. 3 is input to an inverting buffer with a gain of 1 by operational amplifier Q23-4. The level of the measured potential is adjusted by varying the voltage applied to the non-inverting input of Q23-4 using variable resistor VR7. Q23-
The output of 4 varies from 12V in proportion to the change in surface potential.
The signal is input as a low impedance signal varying up to 17V to an A/D converter including operational amplifiers Q23-1, Q23-2, etc. A/ from CPU2
D command signal ADC is normally “H”, and the output of inverter Q16-4 is “L”.
Zero bias is applied between the source and gate of FET switch Q24, conduction occurs between the source and drain of Q24, and the output of operational amplifier Q23-2 is maintained at +12V. The CPU 2 detects the falling edge of the timing pulses V _L CTP, V _D CTP, and υ _L CTP given from the CPU 1, changes the A/D command signal from "H" to "L", and outputs it to the inverter Q16-4. At this time, the output of Q16-4 becomes "H" and a reverse bias is applied to the gate of FET Q24, thereby cutting off Q24. Q
Since +12V is applied to the non-inverting input terminal of 23-2 via the resistor R45-6, when Q24 is cut off, the output of Q23-2 and the capacitor C40,
An integrator circuit loop of resistor R46 is configured and Q-2
The output of 3-2 is set at 12V as the initial voltage, and the current flowing through R46 linearly flows through capacitor C until the A/D command signal becomes "H" and FETQ24 becomes conductive.
Charge 40. When FETQ24 conducts, C40
The charge stored in Q23-2 is discharged through R41-4, and the output of Q23-2 rapidly drops to 12V. After integration is started as described above by the A/D command, after a certain period of time, the CPU 2 starts counting. Start. In order to match this counting start point with the minimum value 12V of the output of Q23-4, the output of Q23-2 is level-shifted by resistors R41-2 and R41-3, and the non-inverted rotation of the operational amplifier Q23-1 that constitutes the comparator is performed. It is input to the input terminal via the resistor 45-7. On the other hand, the measured potential is input to the inverting input of Q23-1 via a resistor R27-6. Q23 while the output voltage of the integrating circuit is lower than the measured potential.
The output of -1 is "L", and counting is performed inside the CPU 2 during this time. When both voltages match, Q23-
The output of 1 becomes "H" and this level change is sent to the interrupt terminal of CPU2 as a counting end pulse via Sienar diode ZD3 and operational amplifier Q21-2.
Input to INT. The CPU 2 processes the internal count value until the end of counting as the measured potential A/D converted value. In this way the timing pulse
Each potential of the bright area potential, dark area potential, and standard bright area potential can be A/D converted in synchronization with each pulse of V _L CTP, V _D CTP, and υ _L CTP. In this embodiment, the CPU 2 is an NMOS 1 chip 8-bit microcomputer (μPD8048C). The signals shown in the table below are input or output to each terminal of the CPU.

【table】

[Table] Signals DMS1, 2, EPC, and DBC from the changeover switch SW1 are input to the terminals DB4 to DB7. The control mode of CPU2 in each signal state is shown in the table below.

[Table] Next, the D/A converter will be explained. The CPU2 and the D/A converter Q18 are connected by four data lines LA0 to LA3 and one control line LDI. At the rise of LDI, the CPU 2 specifies whether the data to be D/A converted is primary current control data, secondary current control data, or developing bias control data using LA0 to LA3.
LA sent from CPU2 at the falling edge of LDI
The data on 0 to LA3 are latched into the D/A converter Q18. D/A converter Q18 connects internally latched data and capacitors C37, C38,
C39, resistor R41-1, 4 bits counted by internal clock oscillated by coil L5,
This is done by detecting a match with a 6-bit or 12-bit binary counter. That is, an analog value is obtained by integrating pulses whose duty varies depending on the data. The D/A output, DAC3 and 4 each have a 4-bit resolution pulse, and DAC1 has a 12-bit resolution pulse.
2 is constructed so that pulses with 6-bit resolution can be obtained respectively. These pulses are connected to resistor R3
9. Converted to an analog voltage by an integrating circuit using a capacitor C34. Further, R36 is a pull-up resistor added because the output is an oven drain. The D/A converted primary current control value is a voltage value equivalent to the upper 4 bits in DAC4 and the lower 4 bits in DAC3. These are the voltage values equivalent to the operational amplifiers Q22-3 and Q2.
R5 after passing through the non-inverting buffer by 2-4
7-1, R35-2, and R35-1 to obtain a voltage value corresponding to 8 bits, which is applied to the No. 1 terminal of the changeover switch SW2. The secondary current control value is converted to a voltage value equivalent to 12 bits and output from DAC1 to operational amplifier Q22-2.
After passing through a non-inverting buffer, it is applied to the No. 1 terminal of the changeover switch SW3. The developing bias control value is integrated and then applied to the first terminal of the changeover switch SW4. Changeover switches SW2, SW3, and SW4 are for CPU2
This circuit is provided to switch between potential control by the CPU 2 and a circuit that causes a reference current to flow through the charger without going through the CPU 2 and sets the developing bias to a predetermined value. By this switching, even in a situation where the CPU 2 is inoperable due to some kind of accident, it is possible to supply a reference current to the charger and set the developing bias to a predetermined value. On the primary side, a voltage that provides a reference current is applied to the second terminal of the changeover switch SW-2 by resistor division through R57-4 and R57-8. On the other hand, for the secondary, there is a signal to switch between AC and weak AC.
Inverter Q16-3 is turned on and off by HVDC. Q16- when HVDC is “H”
3 outputs become “L” and R57-5, R57-6,
The voltage determined by R57-7 is the selector switch.
It is given to the 2nd terminal of SW-3. This voltage is
It is set to provide an AC reference current. next
Q1 when HVDC goes “L” and weak AC flows.
6-3 is turned off and the voltage determined by R57-4 and R57-7 is switched to provide a weak AC current. Regarding the developing bias, R is the same as in the primary case.
57-2, the voltage obtained by resistor division with R30-1 is set as the developing bias reference voltage with the selector switch SW-.
It is given to the 2nd terminal of 4. As described above, when the circuit before the D/A converter malfunctions, the switching means SW2 to SW4 prevent the malfunction from reaching the high-voltage charger and developing bias circuit in the subsequent stage, and furthermore, the high-voltage charger and developing bias circuit are A predetermined value is set so that the circuit outputs a reference current or reference voltage. Therefore, even if the device before the D/A converter fails, image formation can be performed and extreme deterioration of image quality can be prevented. The primary charger control voltage VP is the terminal 1- of SW-2.
3 and is input to the inverting input terminal of operational amplifier Q14-1 via resistor R19-1. Q14-
The voltage V _F p applied to the non-inverting input terminal of No. 1 and the Vp
The voltage difference between Q14-1 is multiplied by -R23/R19-1 and output from Q14-1. When the primary charger drive signal HVDc is “L”, Q20-2 output is “H”, Q16-5
The output becomes "L", diode D12-1 is forward biased and conductive, and Q14-1 output is approximately
It is clamped to 0.6V and the primary charger is turned off.
When the HVDC becomes "H", the Q14-1 output is output to the primary high voltage transformer TDC. The voltage applied to the primary transformer TDC is boosted to the secondary side according to the winding ratio of the transformer, rectified and smoothed by a diode and a capacitor, and then applied to the primary charger 51. The primary corona current Ip flowing through the primary charger 51 is detected by the resistor R11 and R20-4, VR4, R2
Level shifted by 0-3 combination, Q14
-1 non-inverting input terminal via a resistor R19-2, and the primary corona current Ip is controlled so that the voltage V _F p and the primary charger control voltage Vp match. Similarly, AC static eliminator control voltage V _A c is operational amplifier Q1
It is input to the inverting input terminal of No. 4-2 via a resistor R19-4. The difference voltage between the voltage V _FA c applied to the non-inverting input terminal of Q14-2 and the correction voltage V _A c is -
It is multiplied by R24/R19-4 and output from Q14-2. Q2 when AC static eliminator drive signal HVAC is “L”
The 0-7 output becomes "H", the Q16-6 output becomes "L", the diode D12-3 conducts, the output of Q14-2 is clamped to about 0.6V, and the AC static eliminator is off. When the HVAC becomes "H", the Q14-2 output voltage is applied to the AC high voltage transformer TAC. The output, which is boosted to the secondary side according to the winding ratio of the transformer, is rectified and smoothed by a diode and a capacitor, and becomes a DC component output. In addition, the AC high voltage transformer TAC also outputs AC high voltage, and superimposes the DC signal output to create a secondary
Output to AC charger 69. The AC corona current I _A c flowing through the secondary AC charger 69 is detected by the resistor R12. The detection output is amplified by amplifier Q9-1 and then integrated by R14-6 and C38, and then Q9
After being buffered by -2, R20-5,
R20-7, level shifted by VR3 and Q1
AC is input to the non-inverting input terminal of 4-2 so that the above-mentioned V _FA c and the above-mentioned secondary AC correction voltage V _A c match.
Control the corona current I _A c. As described above, the outputs of the high voltage chargers 51 and 69 are blocked by the diodes D _12-1 and D _12-2 . This is shown in the time chart in Figure 11.
During the WET period, the CPU 2 has not been reset and the output of the digital computer is uncertain. The output of the static eliminator is blocked, thereby preventing high-voltage corona discharge from occurring due to an uncertain control voltage during the PRE-WET period, which is extremely undesirable in terms of the image forming cycle. Q15-1 is a buffer circuit, and the output of Q15-1 is obtained by dividing 24V by variable resistor VR1.
The operational amplifier Q14-1 is an inverter, and when the primary charger control signal Vp decreases, the high voltage output current increases. When the primary charger control signal Vp begins to fall below the minimum value, the Q14-1 output increases to the maximum, and therefore the input to the primary high voltage transformer TDC increases to the maximum. Q14 that determines this maximum value
-1 output to a value approximately 1.2V lower than the Q15-1 output.
If the output is adjusted by VR1, when the Q14-2 output attempts to exceed the maximum value, the diodes D12-2 and D13-4 become conductive, and the Q14-2 output will not increase beyond the maximum value. The same applies to the limiter on the AC static eliminator side. The developing bias control signal given to the 1st terminal of SW-4 is inputted from the 3rd terminal to the operational amplifier Q22-1 via the resistor R30-3.
It is amplified with a gain determined by the ratio of VR6 and R30-3, and from the output of Q22-1, transistors Q10 and Q
11 and is applied to the midpoint of the inverter transformer T2. A voltage obtained by dividing 24V by a variable resistor VR5 is applied to the non-inverting input terminal of Q22-1, and by adjusting VR5, the level of the developing bias can be varied. Further, by adjusting the VR6, the gain of the developing bias can be adjusted. When the drum is rotating and no development is being performed, the bias voltage is set to -75V to prevent developer from adhering to the drum. During standby, the bias voltage is set to OV, and when the drum is not rotating,
This prevents the charged liquid developer from stagnation. During development, the development bias value is controlled to be +102V with respect to the standard bright area potential by the development bias control signal from the D/A converter. The developing bias value is obtained by a combination of a variable output inverter transformer T2 whose oscillation output changes depending on the current booster output, and a fixed output inverter transformer T1. Variable output inverter is transistor Q5, Q6
By using a self-excited oscillation inverter, Q5 and Q6 are alternately turned on and off, and the voltage induced on the primary side of T2 in response to the developing bias control voltage applied to the midpoint of T2 is determined by the winding ratio of T2. The voltage is increased to the secondary side voltage, half-wave rectified by D11, smoothed by C27, and the DC high voltage output is supplied to the developing roller via R17. On the other hand, in a fixed output inverter, 24V is applied to the middle point of the primary side of T1, and the secondary high voltage output is output according to the transformer winding ratio.
2. By rectifying and smoothing with C10, a negative fixed DC high voltage is obtained. A divided voltage from the center of resistors R3-1 and R3-2 is superimposed on the output of the variable output inverter, and the developing bias voltage changes linearly from positive to negative in response to the input control voltage. In the fixed output inverter T1, in addition to the fixed output for the developing bias, a -12V power supply, a floating power supply voltage of 24V and 40V to the surface potential measurement circuit, and a -600V power supply voltage to the surface potential measurement circuit are obtained. There is. If these are constructed from ordinary regulators or the like, it will take up space, increase the number of parts, and the floating power supply in particular will become complicated. According to this configuration, the various power supply voltages described above can be obtained extremely efficiently. The microcomputer CPU2 has a built-in program for implementing the surface potential control method described above, and the program flowchart is shown in Part 19.
Shown in Figures A-E. In the flowchart, DC is a digital value for controlling the primary charger, and similarly, AC and DB are digital values for controlling the AC static eliminator and developing bias, respectively. Also, DCSA, ACSA,
DBSA indicates the PAM area in CPU2 where signal digital values DC, AC, and DB are saved. <Step SP1> When the reset signal RESET from CPU1 is input, all memory areas of RAM are cleared and
The input port of CPU2 is enabled for input,
The output port is set to an output enabled state. or
Initialize ACSA, DCSA, and DBSA. or,
The current flowing through the primary charger and AC static eliminator is OμA, and the developing bias voltage is also OV. <Step SP2> It is determined whether the AC static eliminator drive signal HVAC indicating that copying has started is "0" or "1", and if it is "0", the process proceeds to SP23, and if it is "1", the process proceeds to SP3. <SP3> Set the CPU2 port again and output the sensor drive signal. Further, the LED 24 and LED 25 indicating that HVAC and HVDC are "1" are turned on. <SP4> Determine the signal EPC of the changeover switch SW1 and determine whether to output a standard value to the primary charger and AC static eliminator, or a control value based on the detection output of the electrometer. <SP5> Based on the judgment in step SP4, the primary charger,
AC static eliminator reference current or area ACSA, DCSA
Outputs the stored value within. Also, the developing bias is -
Output to 72V. <SP6> Each signal HVAC, HVDC, V _L CTP, V _D CTP,
υ _L Determine CTP and DBTP and proceed to each processing step. In the display subroutine, when the potential display mode or potential display mode is specified, LED1
The potential is displayed in 8 bits from 0 to 17. In the potential measurement mode and the potential display mode, the potential specified by the changeover switch SW1 is transferred to the accumulator in the CPU 2 and displayed on the LEDs 10 to 17. <SP7> When the bright area potential V _L detection signal V _L CTP is output, the light emitting diode LED 20 indicating it lights up.
At the same time, measure V _L and save the measurement results.
After that, calculate (V _L −V _L0 ) and save the calculated value. Next, the signals CS1 and CS2 input to the terminals P26 and P27 of the CPU 2 are judged and the coefficient α ₂ is selected. Two values of α ₂ can be selected depending on CS1 and CS2. Next, calculate and save α ₂ (V _L −V _L0 ), select coefficient β ₂ in the same way as α ₂ , and calculate β ₂
Calculate and save (V _L −V _L0 ). When the above is completed, the light emitting diode LED20 is turned off and the process returns to SP4. <SP8> When the dark potential V _D detection signal V _D CTP is output, the light emitting diode LED 21 indicating it lights up.
Measure V _D and save the measurement results. <SP9> Check switch SW1 to determine whether potential control is enabled or not. If not, proceed to SP17. If there is, proceed to SP10. <SP10> Calculate (V _D −V _D0 ), α ₁ (V _D −V _D0 ), and β ₁ (V D −V _D0 ), and calculate α ₁ (V _{D −V D0} )β ₁ (V _D −V _D0 ) save the calculation results. The coefficients α ₁ and β ₁ are selected by the signals CS1 and CS2 in the same way as α ₂ β ₂ . <SP11> Calculate α ₁ (V _D −V _D0 ) + α ₂ (V _L −V _L0 )=△DC′,
Add to the previous primary charger control current value DC. At this time, DC is 8 bits and △DC' is 16 bits, so we perform the calculation (DC x 8 + △DC') and get DC' (16 bits).
shall be. <SP12> It is determined whether DC' is within the control range, and if there is an overflow, the LED 12 indicating this is lit and DC' is set to a predetermined value. In the case of underflow, the LED 13 indicating this is turned on and DC' is set to a predetermined value. <SP13> Convert DC' (16 bits) to DC (8 bits),
Save to DCSA. <SP14> In order to obtain the AC static eliminator control current value AC' (16 bits), calculate β ₁ (V _D −V _D0 ) + β ₂ (V _L −V _D0 ).
Find AC' (16 bits) and add 8 to the previous control current value AC.
Add. <SP15> Determine whether AC' is within the control range. In the case of overflow, the LED 10 indicating this is turned on and AC' is set to a predetermined value. In the case of underflow, the LED 11 is turned on and AC' is set to a predetermined value. <SP16> Convert AC' (16 bits) to AC (8 bits),
Save to ACSA. <SP17> Find the difference between the dark potential V _D and the bright potential V _L , that is, the contrast CNT. If CNT is below OV or
When the voltage is 396V or less, both LED14 and LED15 are turned on. LED when CNT is above 396V and below 498V
Only 14 is turned on. If CNT is 498V or higher, the LED will not light up. After the above is completed, the LED 21 is turned off. <SP18> When the standard bright area potential υ _L detection signal υ _L CPT is output, the light emitting diode LED 22 lights up and υ _L is measured and saved. Determine whether υ _L is within the controllable range, and if υ _L is −474V or less and υ _L
If is 288V or higher, set the developing bias voltage DB to a predetermined value and save it in the area DBSA. When υ _L is within the controllable range, calculate (υ _L +102V) and save the calculation result to DBSA. When the above steps are completed, the light emitting diode is turned off. <SP19> When development starts, the development bias signal DBTP is output from CPU1, and the light emitting diode LED2
3 lights up. The presence or absence of developing bias control is determined by looking at the signal DBC of the changeover switch SW1, and if there is no control, the developing bias voltage is set to OV. If controlled, the developing bias voltage DB found in SP18 is output. Thereafter, the display subroutine is executed until the signal DBTP becomes "0", and when it becomes "0", the light emitting diode LED 23 is turned off. <SP20> When HVAC is “1” and HVDC is “0”, the rear rotation LSTR is in progress, so the LED indicates that HVDC is “1”.
25 is turned off and the AC is turned off without current flowing through the primary charger.
Apply a weak AC current (60μA) to the static eliminator. <SP21> Determine whether or not it is in potential measurement mode, and if it is not in potential measurement mode, turn off the potential sensor. The display subroutine is repeated until the post-rotation LSTR is completed. If HVDC becomes “1” during post-rotation, return to SP3. <SP22> When HVAC becomes "0", copying is not in progress, so the LED 24 is turned off, the rotation of the primary charger and AC static eliminator is turned off, and the developing bias voltage is set to OV. <SP23> It is determined whether or not it is the potential measurement mode, and when it is the potential measurement mode, the potential sensor is driven and the measured value is displayed on the LEDs 10 to 17. As explained in detail above, in this embodiment, a latent image forming means for forming an electrostatic latent image on a recording medium such as a photosensitive drum, a developing means for developing the latent image,
a measuring means for measuring the surface potential on the recording medium; a first control means storing a program for sequentially controlling the latent image forming means; and forming a latent image in the latent image forming means based on the output of the measuring means. It has a second control means storing a program for controlling the conditions or the development conditions of the measuring means, and the second control means is controlled by a timing signal from the first control means. be. With such a configuration, programs for automatic control systems such as charger control and developing bias control can be developed independently of the development of sequence control programs, and program changes are also facilitated. In addition, the control program for performing sequence control only needs to prepare a very small number of timing signals, and it is possible to program the sequence control separately from the automatic control system. Furthermore, it becomes easy to diagnose failures in each control means such as a microcomputer, and various potential controls can be performed as shown in this embodiment, thereby greatly expanding the functionality. In addition, the microcomputer CPU2 can be switched to the microcomputer CPU2 regardless of the output of the A/D converter using the changeover switch SW1.
Since the digital output value of can be set to a standard value, an image with stable image quality can be obtained even if the electrometer, measurement circuit, or A/D converter fails.

[Brief explanation of the drawing]

FIG. 1a is a sectional view of a copying apparatus to which the present invention can be applied, FIG. 1b is a plan view of the vicinity of the blank exposure lamp, FIG. 2 is a characteristic diagram showing the surface potential of each part of the photosensitive drum, and FIG. Fig. 4 is a characteristic diagram showing changes in surface potential, Fig. 5 is a surface measurement diagram of the surface potential meter, Fig. 6 is a sectional view taken from the right side of the line X-X' in Fig. 5,
Figure 7 is a sectional view taken from the left side of the line X-X' in Figure 5, Figure 8 is a perspective view of the electrometer, Figures 9a and b are diagrams showing changes in dark area surface potential, and Figure 10a. 10 is a schematic cross-sectional view of a copying apparatus regarding developing bias control;
Figure b is a lighting control circuit diagram of the original exposure lamp, No. 11.
The figure shows a time chart for image formation and surface potential control, Figure 12 is a block diagram of the potential measurement circuit, Figures 13 to 16 are detailed circuit diagrams of each part of Figure 12, and Figure 17 is the clamp circuit. 18 is a circuit diagram of the potential control unit, and FIGS. 19A to 19E are diagrams showing program flowcharts stored in the CPU 2. In the figure, 47 is a photosensitive drum, 51 is a primary charger, 69 is an AC charger, 70 is a blank exposure lamp, 65 is a developing roller, 67 is a surface electrometer,
CPU1 is a microcomputer for sequence control, CPU2 is a microcomputer for potential control,
Q18 each indicates a D/A converter.

Claims (1)

[Scope of Claims] 1. An image forming means comprising a plurality of process means for forming an image on a photoreceptor, a detection means for detecting a surface potential of the photoreceptor, a step of detecting the surface potential of the photoreceptor by the detection means; and a control step for controlling the output of a specific process means among the plurality of process means based on the surface potential detected in the detection step, and by executing the program, the photoreceptor is a first digital computer that optimizes the surface potential; and a first digital computer that sequentially controls the image forming means, and further outputs a timing signal for instructing the first digital computer to detect the surface potential of the photoreceptor. a second digital computer; the first digital computer is connected to the second digital computer;
Initialization is performed by inputting a reset signal from the digital computer, and furthermore, when it is determined that the timing signal has been input from the second digital computer after the initialization, the detection is performed independently of the sequence control by the second digital computer. An image forming apparatus characterized in that the image forming apparatus executes the step and the control step.