JPH0253639U - - Google Patents

Info

Publication number
JPH0253639U
JPH0253639U JP1988131482U JP13148288U JPH0253639U JP H0253639 U JPH0253639 U JP H0253639U JP 1988131482 U JP1988131482 U JP 1988131482U JP 13148288 U JP13148288 U JP 13148288U JP H0253639 U JPH0253639 U JP H0253639U
Authority
JP
Japan
Prior art keywords
agc voltage
display
level
signal
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1988131482U
Other languages
Japanese (ja)
Other versions
JPH0644189Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988131482U priority Critical patent/JPH0644189Y2/en
Publication of JPH0253639U publication Critical patent/JPH0253639U/ja
Application granted granted Critical
Publication of JPH0644189Y2 publication Critical patent/JPH0644189Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Monitoring And Testing Of Transmission In General (AREA)
  • Circuits Of Receivers In General (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の第1実施例のブロツク回路図
である。第2図は本考案の第2実施例のブロツク
回路図であり、第3図はその表示形態を示す図で
ある。第4図は従来例のブロツク回路図である。 6……第2中間周波増幅回路(AGC電圧発生
手段)、6′……AGC電圧発生回路、13……
判定回路、16……マイクロコンピユータ、18
……ラツチ回路、21……管面表示制御回路、2
2……ブラウン管、23……PCMデコーダ、2
4……マイクロコンピユータ、27……オンスク
リーン表示用IC。
FIG. 1 is a block circuit diagram of a first embodiment of the present invention. FIG. 2 is a block circuit diagram of a second embodiment of the present invention, and FIG. 3 is a diagram showing its display form. FIG. 4 is a block circuit diagram of a conventional example. 6... Second intermediate frequency amplification circuit (AGC voltage generation means), 6'... AGC voltage generation circuit, 13...
Judgment circuit, 16...Microcomputer, 18
... Latch circuit, 21 ... Screen display control circuit, 2
2... Braun tube, 23... PCM decoder, 2
4... Microcomputer, 27... On-screen display IC.

Claims (1)

【実用新案登録請求の範囲】 (1) 入力信号レベルに応じたAGC電圧を発生
するAGC電圧発生手段と、入力信号中の映像信
号の有無を判定する判定回路と、該判定回路によ
つて映像信号が無いと判定された場合の判定出力
によつて前記AGC電圧をラツチするラツチ回路
と、前記ラツチされたAGC電圧を基準にして前
記AGC電圧発生手段からのAGC電圧に基づい
た表示を表示手段に行わせる表示制御回路と、か
ら成るBSアンテナ入力レベル表示装置。 (2) 入力信号レベルに応じたAGC電圧を発生
するAGC電圧発生手段と、入力信号から得られ
たPCMデータが正常でない場合に同期はずれ信
号を出力する同期はずれ信号発生手段と、前記A
GC電圧に基づいた入力信号レベル表示を行うた
めの表示手段と、前記同期はずれ信号が出力され
たとき表示レベルを所定の小さな値又は量になし
同期はずれ信号が解除された場合にその解除され
た時点のAGC電圧を基準にしてAGC電圧に基
づいた表示を行わせる表示制御手段と、から成る
BSアンテナ入力レベル表示装置。
[Claims for Utility Model Registration] (1) AGC voltage generation means that generates an AGC voltage according to the input signal level; a determination circuit that determines the presence or absence of a video signal in the input signal; A latch circuit that latches the AGC voltage according to a determination output when it is determined that there is no signal; and a display means that displays a display based on the AGC voltage from the AGC voltage generation means with the latched AGC voltage as a reference. A BS antenna input level display device comprising: a display control circuit for controlling a signal; (2) AGC voltage generation means for generating an AGC voltage according to the input signal level; an out-of-synchronization signal generation means for outputting an out-of-synchronization signal when the PCM data obtained from the input signal is not normal;
A display means for displaying an input signal level based on a GC voltage, and a display means for setting the display level to a predetermined small value or amount when the out-of-synchronization signal is output, and setting the display level to a predetermined small value or amount when the out-of-synchronization signal is released. A BS antenna input level display device comprising: display control means for performing a display based on the AGC voltage with the current AGC voltage as a reference;
JP1988131482U 1988-10-07 1988-10-07 BS antenna input level display device Expired - Lifetime JPH0644189Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988131482U JPH0644189Y2 (en) 1988-10-07 1988-10-07 BS antenna input level display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988131482U JPH0644189Y2 (en) 1988-10-07 1988-10-07 BS antenna input level display device

Publications (2)

Publication Number Publication Date
JPH0253639U true JPH0253639U (en) 1990-04-18
JPH0644189Y2 JPH0644189Y2 (en) 1994-11-14

Family

ID=31387594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988131482U Expired - Lifetime JPH0644189Y2 (en) 1988-10-07 1988-10-07 BS antenna input level display device

Country Status (1)

Country Link
JP (1) JPH0644189Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6229223A (en) * 1985-07-29 1987-02-07 Sony Corp Receiver

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6229223A (en) * 1985-07-29 1987-02-07 Sony Corp Receiver

Also Published As

Publication number Publication date
JPH0644189Y2 (en) 1994-11-14

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