JPH0251976A - Image signal processing system - Google Patents

Abstract

PURPOSE:To remove noise components to an output image at the time of switching and to obtain the output image with a good quality by obtaining the synchronization of a picture tone switching signal and a pattern signal received from an external part. CONSTITUTION:A switching signal 2101 to indicate an area change from a reader read in synchronizing from a buffer memory 2105 and video data 2100 are inputted to a look-up table 2106, respectively, and a gamma characteristic is switched according to a picture tone. On the other hand, an original signal SCLK of a pattern generation outputted from a synchronization control circuit 2113 is outputted as a pattern signal TVCLK having the same synchronization as an image frequency and a PVCLK with a period to be 1/2-fold by a frequency-dividing circuit 2114. By using the pattern signal TVCLK for the clock of a flip-flop 2102, a picture quality deterioration due to a synchronization shift between the video data and pattern clock due to the delay of the circuit is prevented. Thus, the turbulence of a video signal at the time of switching according to the picture tone is eliminated, and the image with the good quality can be obtained.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an image signal processing method for obtaining a binary image signal using pulse width modulation, and in particular, for processing of image tones such as halftone drawings and line drawings. This invention relates to an improvement in preventing image disturbances caused by changes in modulation frequency at image tone conversion points in image signals of images in which different signals are mixed.

[Prior Art] When a digital image signal is binarized and image formed using a laser beam printer, for example, the digital image signal is converted to an analog signal in order to obtain halftone gradation. A method has been proposed in which a pulse width modulated binary signal is generated by comparing the signal with a periodic pattern signal such as a triangular wave. Furthermore, in order to obtain the optimal output image by adjusting the image tone for each area of halftone images and line drawing images that are mixed on the same original, it has multiple pattern signals. An image forming apparatus has also been proposed in which a plurality of converted binary signals are switched depending on the image tone, such as a halftone portion or a line drawing portion.

FIG. 6 shows a specific example of this latter method. First, image data read from a league section (not shown) is sent to the printer as 8-bit image data 2100. This image signal is the horizontal synchronization signal RH on the reader side.
The signal is input to the buffer memory 2105 in synchronization with 3YNC and video clock RCLK.

The image data stored in the buffer memory 2105 is successively output from the buffer memory 2105 in synchronization with the H3YNC and CLK signals from the synchronization control unit 2113. This causes synchronization deviation and speed conversion between the league section and the printer section (not shown). The read signal is input to LUT (lookup table) 2106. This LUT
Reference numeral 2106 denotes a density converter having γ characteristics, which corrects the 8-bit image signal from the reader so that the density becomes linear in accordance with the output characteristics of the printer. The converted 8-bit image signal is converted into an analog signal by the D/A converter 2107, and is input to one input terminal of the comparators 2117 and 2118.

A pattern signal for binarizing the video signal (PWM modulation) is input to the other input terminals of the comparators 2117 and 2118. The pattern signal to the comparator 2117 is for line drawing or halftone dot generation.
Since resolution is important, the frequency is the same as that of the video signal (400 lines in this example), and a pattern signal is generated for each pixel. Also, since the pattern signal to the comparator 2118 is for a halftone image, it is necessary to increase the gradation, so the frequency is 1/2 that of the pattern signal for the line drawing signal (200 lines in this example). The settings are as follows.

Here, a method of generating the pattern signal described above will be described.

Photoreceptor (not shown) is scanned by laser beam.
As is well known in a digital copying machine that scans the image to obtain a copy by an electrophotographic process, a synchronization signal in the main scanning direction is obtained by the BD detection circuit 2111. This BD double signal, a master clock signal from the crystal oscillator 2112 with a frequency four times higher than the image signal, and an ITOP signal, which is a vertical synchronization signal in the sub-scanning direction, are input to a synchronization control circuit 2113, and a horizontal synchronization signal is HSYNC, vertical synchronization signal ITOP, and video clock (VCLK) are synchronized. Furthermore, a crystal oscillator (XTAL) 211
The master clock signal from 2114 is input to the frequency divider circuit 2114, and the master clock signal from PV
CLK is obtained. That is, in the frequency dividing circuit 2114, the master clock is frequency-divided to have the same frequency as the video clock for TVCLK, and to 1/2 the frequency of the video clock for PVCLK. TVCLK and PV
CLK is input to each of pattern generation circuits 2115 and 2116, respectively. Pattern generation circuit 2115.211
6, an analog pattern signal of a predetermined period (e in Figure 7)
, h) are generated. In the conventional example currently being described, this pattern signal is a triangular wave pattern signal. This 2
The two pattern signals are connected to comparators 2117 and 211.
8, and here, the D/A converter 2
107 and is compared with the analog video signal which has been converted into an analog value. That is, comparator 211
The output from 7, 2118 is two systems of pulse width modulation signals 2
126 and 2127, and selector 2119 respectively.
is input to the input terminal of

The selector signal of the selector 2119 is a latched switching signal 2101 from a league section (not shown). That is, the switching signal 2101 is transmitted to the printer section as a region signal indicating either a line drawing or an intermediate image for each pixel of the video signal. This switching signal 210
1 is a buffer memory 21 for speed conversion with the league part.
05 is input. Thereafter, after being read from the buffer memory, it is synchronized with the video data by a flip-flop (F/F) 2102 and input as a signal to the B terminal of the selector 2119.

Here, when the switching signal 2101 is "1", the signal at the B terminal of the selector 2119, that is, the 200 line is selected, and an output image suitable for the halftone area is selected. Further, when the switching signal 21o1 is "0", the signal at the A terminal of the selector 2119, that is, the 4°O line is selected, resulting in an output image suitable for the line drawing area.

As described above, the gate circuit 2120 inputs the video signal selected according to the image tone of the original to the laser driver 2121 in a state where the output position is matched with the output paper. Then, the semiconductor laser 2122 is driven with a constant current for an ON time corresponding to the pulse width of the input video signal, and a photoreceptor (not shown) is scanned to obtain a copy original through an electrophotographic process.

[Problems to be Solved by the Invention] However, the following problems occur in the above conventional example.

In other words, the synchronization between the signals of pattern clock 1 and pattern clock 2 may be lost due to variations in IC elements or patterns. As the difference increases, the difference becomes larger, and at the input positions of the comparators 2117 and 2118, it becomes effective as a phase shift between the signals.

Triangular wave pattern signal 1.2 is pattern clock 1, 2
Since the pattern signals 1 and 2 are generated from , the phase relationship of the pattern signals 1 and 2 is also distorted. When this pattern signal 1.2 is used to convert the analog signal into a binary value, the resulting PWM signals 1 and 2 are close to each other, but do not overlap, as shown as t+ and ti in Figure 7. Obtained as a signal. These PWM signals 1 and 2 are then input to the selector 2119. It is assumed that the video signal (=image signal) inputted in FIG. 7 is a signal of 00H (=white) so that the problems of the prior art can be well understood.

Consider a case where switching signal 2101 is input when the relationship shown in FIG. 4 exists. In this case, for matching with the video signal, the switching signal 2101 is
The flip-flop 2102 in FIG. 6 latches the out-of-phase video clock (VCLK) at the rising edge, and the Q output of the flip-flop 2102 is input to the select signal of the selector 2119. Then, the change point of the Q output of the flip-flop 2102 is t
1 signal and before the t2 signal, so the selector 2119 selects both t+ and tz before and after the change point of the Q output of the flip-flop 2102.
The video signal 21o3, which is the output of the selector 2119, is a combination of the PWM signal 1 and the pulses of the PWM signal 2, that is, 1. +1. This becomes a pulse signal with a time width of t++t, which is input to the laser driver 2121, and
The laser is turned off for z time.

Generally, in the electrophotographic process of binarization using pulse width modulation using a triangular wave, the intensity of the laser beam is set as follows. That is, when the input image signal is white (=00□), the time width of the pulse signal t1 of PWM signal 1 and the pulse time t2 of PWM signal 2, if each exists independently, will be different from the electrophotographic process. The pulse width is adjusted so that even if the laser beam is irradiated onto the photoreceptor, the pulse width will not become apparent due to the developer.

However, as explained in FIG. 7 above, with the pulse width (1, +12) synthesized at the time of cutting change, even the video signal (00) part (i.e., the white part) becomes visible due to the developer. . This has the disadvantage that when looking at the output image, black dots appear during switching, resulting in a very noisy image quality.

Furthermore, the prior art also has the following problems. In other words, even if you prioritize gradation for 200 lines and resolution for 400 lines, as long as the density is converted using the same LUT,
The drawback of not being able to obtain high-quality images remains.

The present invention was proposed in order to eliminate the above-mentioned problems of the prior art, and its purpose is to convert image signals from originals containing images of different tones when binarizing image signals by pulse width modulation. In this paper, we propose an image signal processing method that processes images without generating noise.

Another object of the present invention is to perform image signal processing to binarize an image signal from a document containing images of different image tones in accordance with the image tone when the image signal is binarized by pulse width modulation. This paper proposes a method.

[Means for Achieving the Object] In order to achieve the object, the present invention provides a pulse width modulation means that compares an input image signal with a pattern signal having a predetermined period and performs pulse width modulation on the image signal. An image signal processing system comprising: the pulse width modulation means having a plurality of patterns of the pattern signals, and further comprising: an output means for outputting a signal instructing switching of the image tone of the input image signal; and synchronization means for synchronizing the pattern signal with the pattern signal.

In such a configuration, if the instruction signal is synchronized with the pattern signal, noise will no longer occur.

The present invention according to another configuration includes means for performing density conversion processing on an input image signal, and pulse width modulation for performing pulse width modulation by comparing the image signal after density conversion with a pattern signal having a predetermined period. The image forming apparatus is characterized by comprising: a means for outputting a signal instructing switching of the image tone of the input image signal; and a means for switching the density converting means in accordance with the instruction signal.

In this configuration, density conversion according to the number of lines is performed by pulse width modulation.

[Example] Hereinafter, two examples of the present invention will be described with reference to the accompanying drawings. Characteristic features of these embodiments are that the video clock (BCLK) and the pattern signal can be synchronized and density conversion can be performed according to the number of lines.

Hereinafter, two embodiments of the present invention will be described with reference to the accompanying drawings. These two embodiments incorporate both of the above two features.

11 m A first embodiment of the present invention will be described in detail based on FIG.

Components with the same numbers as in FIG. 3 have the same functions, so their explanation will be omitted.

A video signal from a reader section (not shown) is inputted to comparators 2117 and 2118 through a path similar to that shown in FIG. 3, where it is pulse width modulated and drives a semiconductor laser 2122 at a constant current as a binary signal. A laser beam from this laser scans a photoreceptor (not shown), and a copy original is obtained by an electrophotographic process.

Horizontal synchronization signal BD generated in synchronization control block 2113, blanking signal 2125 for this signal BD, pattern generation signal 5cLK, two pattern clock signals TVCLK, PVCLK, video clock signal VCLK, etc. 5th timing chart
As shown in the figure.

In FIG. 1, a clock signal from a crystal oscillator 2112 with a period four times or more than the image clock is sent to a synchronization circuit 2122.
is input. This synchronization control circuit 2113 outputs the image clock VCLK synchronized with the horizontal synchronization signal BD, vertical synchronization signal ITOP signal, etc., the H3YNC signal used for horizontal synchronization of logic, and the 5CLK signal which is the original signal of the pattern signal. are output respectively. Here, the original signal 5CL of pattern generation is output in synchronization with twice the image signal.
The K signal is divided into TVCLK, which has a period equal to the image frequency, and P, which has a period 1/2 times the image frequency, in a frequency dividing circuit 2114.
VCLK and VCLK, each is output as a pattern signal with a duty ratio of 50%.

The blanking signal 2125 is the output of a counter (not shown) that is reset at the falling edge of the BD double signal and is set after a period of time slightly shorter than the BD signal period. Here, a switching signal 21o1 indicating an area change from the reader is written into the buffer memory 2105 in synchronization with the video data 2100, and a horizontal synchronizing signal H3Y
It is read out in synchronization with the NC and video clock VCLK and at the same coordinates as the video signal.

The switching signal 2101 and video data 2100 read out synchronously from the buffer memory 2105 are respectively input to the LUT 2106;
The latter is connected to the upper address, and the latter to the lower address.

By inputting the switching signal 2101 to the upper address of the LUT 2106, the γ characteristic is switched according to the image tone, and the density conversion that matches the number of lines, that is, the image tone, is performed here. In other words, at the change point of the switching signal, γ conversion is performed so that the density becomes thinner, resulting in weakening of the black noise at the change point of the switching signal, which was a problem with the prior art described above.

On the other hand, flip-flop 2102 is synchronized with video data. The first embodiment shown in FIG. 1 is configured such that the clock input of this flip-flop 2102 is pattern clock 1 (TVCLK) and the switching signal 2101 is latched at its rising edge. That is, by using TVCLK as the clock for the flip-flop 2102, it is intended to prevent image quality deterioration due to a synchronization difference between video data and a pattern clock caused by circuit delay.

This point will be explained in detail with reference to FIG. As shown in the figure, pattern clock 1 (TVCLK)
Since the switching signal 2101 is latched at the rising edge of , the latching to the flip-flop 2102 is delayed. That is, the latch timing is after t2. Since the Q output of the flip-flop 2102 is the selection signal of the selector 2119, if the latch timing is later than t2, only the pulse t1 is selected before the latch timing, and the pulse t2 is not selected after the latch timing. Therefore, as shown in FIG. 2, since the output of the selector 2109 is a pulse within a specified width, the pulse width will not become apparent due to the developer. That is, there is no disturbance in the video signal when switching according to the image tone, and a high quality image can now be obtained.

Furthermore, since the addresses of 2106LUT2 are switched at the same timing, it is now possible to obtain high-quality images in accordance with the output characteristics according to the number of lines.

As will be understood with reference to FIG. 2, the latch to the flipflop 2102 may be synchronized with the video data at the rising edge 2102 of TVCLK. Alternatively, PVCLK may be used.

A second embodiment of the present invention is shown in FIG. The first embodiment described above is intended to compensate for the phase shift by forcibly synchronizing the switching signal with the pattern signal or pattern clock and leaving the phase shift as it is.Second embodiment is the phase of VCLK itself, TVCLK and PV
In anticipation of a discrepancy between CLK and (7), it is intended to be shifted from the beginning.

A switching signal from a reader unit (not shown) is once input to the buffer memory 2105 as explained in FIG. Thereafter, it is read out in synchronization with the H5YNC video clock VCLK. Then flip-flop.

The clock input of this flip-flop 2102 is V
CLK is determined as follows. As previously mentioned, 4:
:, TVCLK and PVCLK or pattern signal 1 and pattern signal 2 are shifted in phase, but the amount of shift is fixed depending on the circuit. Therefore, in anticipation of this amount of deviation, the synchronization control circuit 2113 attempts to move VCLK forward and backward.

The switching operation in this second embodiment will be explained in detail using FIG. 4. VCLK input to the flip-flop 2102 is advanced in phase as shown in FIG. 4, as described above. In the example in Figure 4, TVCLK and PV
CLK is phase-shifted to such an extent that tl and t2 occur in the phase relationship shown in the figure. Therefore, V
The degree to which CLK is advanced is determined by the latch timing tl and t2.
If t2 is located between the video signal 2 and
103, there is no disturbance in the video signal when switching according to the image tone, and high-quality image lines can be obtained.

Now, the switching signal read out from PIF○2105 in synchronization with HSYNC and video clock VCLK is connected to the select input of selector 2130. “FF” is input to the other input of the selector 2130.

When this switching signal indicates that the image quality emphasizes gradation, it is set to select the video signal that has passed through LUT 2106, and when it indicates that the image quality emphasizes resolution, , select “FF”. By doing this, when the number of lines is 200, the gradation is good, and when the number of lines is 400, by emphasizing the resolution, a high-quality image can be obtained.

As explained above, in order to switch the pulse width modulated binary signal according to the image quality in real time, by taking the cycle of the switching signal and pattern signal received from the outside,
It has become possible to remove noise components from the output image at the time of switching, and it has become possible to provide a high quality output image, making it possible to provide a high quality output image. Furthermore, since the density conversion means is switched according to the number of lines, it is now possible to obtain high-quality images with optimal output characteristics.

[Effects of the Invention] As explained above, according to the image signal processing method of the present invention, an input image signal is compared with a pattern signal having a predetermined period, and pulse width modulation is performed on the image signal. an image signal processing method comprising means, wherein the pulse width modulation means includes a plurality of the pattern signals, and further includes an output means for outputting a signal instructing switching of the image tone of the input image signal; Since the apparatus includes synchronizing means for synchronizing a signal with the pattern signal, the signal detecting the change in image tone is synchronized with the pattern signal.

Due to this synchronization, noise no longer occurs.

The present invention according to another configuration includes means for performing density conversion processing on an input image signal, and pulse width modulation for performing pulse width modulation by comparing the image signal after density conversion with a pattern signal having a predetermined period. the output means for outputting a signal instructing switching of the image tone of the input image signal; and means for switching the density conversion means using this instruction signal; A conversion takes place.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the configuration of the first embodiment, Fig. 2 is a timing chart explaining the operation of the first embodiment, Fig. 3 is a diagram showing the configuration of the second embodiment, and Fig. 4 is a diagram showing the configuration of the second embodiment. A timing chart explaining the operation of the embodiment, FIG. 5 is a timing chart showing the timing in the synchronous control section, FIG. 6 is a diagram showing the configuration of the conventional technology, and FIG. 7 is a timing chart showing the conventional switching timing. It is.

Claims (4)

[Claims] (1) An image signal processing method comprising a pulse width modulation means that compares an input image signal with a pattern signal having a predetermined period and performs pulse width modulation on the image signal, the pulse width modulation means An image signal comprising a plurality of the pattern signals, further comprising an output means for outputting a signal for instructing switching of the image tone of the input image signal, and a synchronization means for synchronizing the instruction signal with the pattern signal. Processing method. (2) A claim further comprising means for selecting one of modulation signals obtained by pulse width modulating the input image signal using a plurality of pattern signals in accordance with the synchronized instruction signal. The image signal processing method according to item 1 of item 1. (3) Further comprising means for selecting one of the plurality of pattern signals according to the synchronized instruction signal and pulse width modulating the analog image signal with the selected pattern signal. The first claim characterized in
The image signal processing method described in . (4) means for performing density conversion processing on an input image signal; pulse width modulation means for performing pulse width modulation by comparing the density-converted image signal with a pattern signal having a predetermined period; and the input image signal. An image signal processing method comprising: means for outputting a signal instructing switching of image tone; and means for switching density converting means using the instruction signal.