JPH0250712B2 - - Google Patents
Info
- Publication number
- JPH0250712B2 JPH0250712B2 JP56174564A JP17456481A JPH0250712B2 JP H0250712 B2 JPH0250712 B2 JP H0250712B2 JP 56174564 A JP56174564 A JP 56174564A JP 17456481 A JP17456481 A JP 17456481A JP H0250712 B2 JPH0250712 B2 JP H0250712B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- waveform
- drive
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005540 biological transmission Effects 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 238000009499 grossing Methods 0.000 description 6
- 230000005284 excitation Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000010349 pulsation Effects 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Description
【発明の詳細な説明】 本発明はDC−DCコンバータに関する。[Detailed description of the invention] The present invention relates to a DC-DC converter.
第１図に従来のDC−DCコンバータの一例を示
し、スイツチングトランジスタ１のオン期間に電
源２の電圧Ｅをトランス３に供給して、出力側へ
電力を供給する。いわゆる電圧伝送形一方向駆動
のDC−DCコンバータである。動作波形を第２図
に示し、同図ａはスイツチングトランジスタ１の
駆動電圧波形、同図ｂは出力捲線の電流波形であ
る。このDC−DCコンバータにおいては、オン時
にトランス３に蓄積した励磁エネルギをオフ時に
完成放出する必要から、オンデユーテイ比を0.5
以下の設定するのが普通である。従つて、出力電
流波形には脈流を生ずるため、コンデンサ５を設
けて平滑する必要がある。ここで、コンデンサ５
の必要な容量は出力電流の脈流が大きい程、ある
いは、出力直流電圧に含まれるリツプル電圧を小
さくしたい程大容量が必要となる。例えば電話端
末内の電源のように、長距離の加入者線を介する
ような高抵抗電圧源から給電を受け、かつ高速に
出力電圧の立上げが要求される場合、平滑コンデ
ンサ５の容量の極小化を要求されるが、従来例で
は満足し得ない欠点があつた。 FIG. 1 shows an example of a conventional DC-DC converter, in which a voltage E from a power source 2 is supplied to a transformer 3 during an on-period of a switching transistor 1, thereby supplying power to the output side. This is a so-called voltage transmission type unidirectional drive DC-DC converter. The operating waveforms are shown in FIG. 2, where a shows the drive voltage waveform of the switching transistor 1, and b shows the current waveform of the output winding. In this DC-DC converter, the on-duty ratio is set to 0.5 because it is necessary to fully release the excitation energy accumulated in the transformer 3 when it is turned on and when it is turned off.
The following settings are common. Therefore, since ripples occur in the output current waveform, it is necessary to provide a capacitor 5 to smooth it. Here, capacitor 5
The larger the pulsation of the output current, or the smaller the ripple voltage included in the output DC voltage, the larger the required capacity becomes. For example, when power is supplied from a high-resistance voltage source such as a power supply in a telephone terminal via a long-distance subscriber line, and the output voltage is required to rise quickly, the capacitance of the smoothing capacitor 5 is extremely small. However, conventional examples have drawbacks that cannot be satisfied.
本発明の目的は、従来技術の欠点をなくし、十
分なリツプル電圧減衰量を得て、かつ高速起動し
うるDC−DCコンバータを提供するにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a DC-DC converter that eliminates the drawbacks of the prior art, obtains sufficient ripple voltage attenuation, and can start up at high speed.
本発明においては、複数のDC−DCコンバータ
を並列接続し、それらの駆動位相をずらし、各相
の出出力電流の総和において脈流が減るようにス
イツチングトランジスタ駆動タイミングを適量重
ねて、結果的に平滑コンデンサの容量を小さくて
済ませるようになしてDC−DCコンバータを高速
起動せしめるようになしたことを特徴とする。 In the present invention, multiple DC-DC converters are connected in parallel, their drive phases are shifted, and the switching transistor drive timings are overlapped by an appropriate amount so that ripple current is reduced in the sum of the output current of each phase. The present invention is characterized in that the DC-DC converter can be started up at high speed by reducing the capacitance of the smoothing capacitor.
以下図面に示した実施例によつて本発明を詳細
に説明する。 The present invention will be explained in detail below with reference to embodiments shown in the drawings.
本発明の実施例を第３図に示す。第３図は、多
相化を３相で実施した例で、各相の出力をダイオ
ードオア１４ａ，１４ｂ，１４ｃで合成したもの
である。各相の駆動電圧e1、e2、e3は、第４図
イ，ロ，ハに示す如く、Δtの重なりが設けられ
それぞれのスイツチングトランジスタ１１ａ，１
１ｂ，１１ｃを駆動する。コンデンサ１５を平滑
手段とした各相の出力電流i1、i2、i3は、第４図
ニに示すごとく、重なりあい、電流の切替えはゆ
るやかな傾斜で切りかわり、和が一定になるよう
に動作する。 An embodiment of the invention is shown in FIG. FIG. 3 shows an example in which multiphase is implemented in three phases, and the outputs of each phase are combined by diode ORs 14a, 14b, and 14c. The driving voltages e 1 , e 2 , e 3 of each phase are overlapped by Δt as shown in FIG.
1b and 11c. The output currents i 1 , i 2 , i 3 of each phase using the capacitor 15 as a smoothing means overlap as shown in FIG. works.
このように本発明は、コンデンサによる平滑の
ため（コンデンサインプツト）、切りかわり点の
電流変化量di／dtが小さく出来、雑音の発生が少く
ない。更に出力電流の総和の脈流が小さいため、
平滑コンデンサの容量が少くなくてすみ、高速起
動が可能となるものである。 As described above, in the present invention, since smoothing is performed by a capacitor (capacitor input), the amount of current change di/dt at the switching point can be made small, and noise generation is not small. Furthermore, since the ripple current of the total output current is small,
The capacitance of the smoothing capacitor does not need to be small, and high-speed startup is possible.
第５図は、上述した動作をなさしめるためのス
イツチングトランジスタ１１ａ，１１ｂ，１１ｃ
の駆動回路の一実施例であり、パルス発振器２
１、１／ｎ分周器２２及び1/3分周器２３が３相
駆動に共通の要素として設けられ、上記1/3分周
器２３と各相のスイツチングトランジスタ１１
ａ，１１ｂ，１１ｃとの間には、相毎にシフトレ
ジスタ２４（２４ａ，２４ｂ，２４ｃ）をオア回
路２５（２５ａ，２５ｂ，２５ｃ）が設けられ
る。第６図は第５図の要部波形図を示し、以下第
５図及び第６図を用いて各相のスイツチングトラ
ンジスタの駆動方法について説明する。 FIG. 5 shows switching transistors 11a, 11b, 11c for performing the above-mentioned operation.
This is an example of the drive circuit of the pulse oscillator 2.
A 1/1/n frequency divider 22 and a 1/3 frequency divider 23 are provided as common elements for three-phase drive, and the 1/3 frequency divider 23 and the switching transistor 11 of each phase
A, 11b, 11c are provided with a shift register 24 (24a, 24b, 24c) and an OR circuit 25 (25a, 25b, 25c) for each phase. FIG. 6 shows a waveform diagram of the main part of FIG. 5, and the method of driving the switching transistors of each phase will be explained below with reference to FIGS. 5 and 6.
第６図ａに示すパルス発振器２１の出力ａから
１／ｎ分周器２２及び1/3分周器２３によつて第
６図ｂ，ｃ，ｄに示す３種の矩形波(b)、(c)、(d)が
生成される。ここで矩形波(b)は、シフトレジスタ
２４ａに入力されるとともにオア回路２５ａの一
方の入力端子にも入力されている。 Three types of rectangular waves (b) shown in FIG. 6 b, c, and d are generated from the output a of the pulse oscillator 21 shown in FIG. 6 a by the 1/n frequency divider 22 and the 1/3 frequency divider 23, (c) and (d) are generated. Here, the rectangular wave (b) is input to the shift register 24a and also to one input terminal of the OR circuit 25a.
上記シフトレジスタ２４ａの出力は上記オア回
路２５ａの他方の入力端子に入力されるが、ここ
でシフトレジスタ２４ａは、パルス発振器２１の
出力(a)によつて読出しが制御され、例えば出力(a)
の１周期分のタイミング遅れで読出しが制御され
るならば、シフトレジスタ２４ａの出力として第
６図ｅの矩形波が得られる。従つてオア回路２５
ａの出力としては、上記矩形波(b)と(e)とのオアを
とつた第６図ｆに示す矩形波が得られ、この矩形
波ｆによつてスイツチングトランジスタ１１ａは
オン制御される。 The output of the shift register 24a is input to the other input terminal of the OR circuit 25a, and the readout of the shift register 24a is controlled by the output (a) of the pulse oscillator 21, for example, the output (a)
If the readout is controlled with a timing delay of one period, the rectangular wave shown in FIG. 6e will be obtained as the output of the shift register 24a. Therefore, OR circuit 25
As the output of a, a rectangular wave shown in FIG. .
スイツチングトランジスタ１１ｂ，１１ｃにも
同様にそれぞれシフトレジスタ２４ｂ，２４ｃ及
びオア回路２５ｂ，２５ｃ（図示略）が設けられ、
両トランジスタ１１ｂ，１１ｃはそれぞれ第６図
に示した矩形波(g)、(h)によつてオン制御される。 Switching transistors 11b and 11c are similarly provided with shift registers 24b and 24c and OR circuits 25b and 25c (not shown), respectively.
Both transistors 11b and 11c are turned on by rectangular waves (g) and (h) shown in FIG. 6, respectively.
従つて各相のスイツチングトランジスタ１１
ａ，１１ｂ，１１ｃは、各相間で上記シフトレジ
スタの読み出し制御分だけスイツチング時間
（Δt）が重畳した形でオン制御されることにな
り、第４図に示した特性が得られることになるも
のである。なお上記Δtは、３相出力電流の総和
波形に重畳過多による凸部または重畳過少による
凹部がないように設定されることは勿論である。 Therefore, the switching transistor 11 of each phase
A, 11b, and 11c are controlled to be turned on in such a way that the switching time (Δt) is superimposed by the amount of the readout control of the shift register between each phase, and the characteristics shown in Fig. 4 are obtained. It is. It goes without saying that Δt is set so that the total waveform of the three-phase output currents does not have a convex portion due to excessive superimposition or a concave portion due to insufficient superimposition.
以上本発明を詳しく説明したが、従来例の場
合、50％オン50％オフの脈流に対し、本発明を用
いたものは第３図の構成で0.5％程度の脈流にお
さまるため（重ね合わせの傾斜のバラツキによ
る、わずかな脈流）、平滑コンデンサの容量は1/1
００程度の小さなものでよく、逆に起動時間は1/10
０の高速化が出来ることとなり、電流特性の優れ
たまた電源立上りの優れたDC−DCコンバータが
提供でき、特に端末機用の電源として大きな効果
を発揮するものである。 Although the present invention has been explained in detail above, in the case of the conventional example, the pulsating flow is 50% on and 50% off, whereas in the case of the present invention, the pulsating flow is reduced to about 0.5% with the configuration shown in Fig. 3 (overlap flow). Slight pulsating current due to variations in the alignment slope), the capacity of the smoothing capacitor is 1/1
A small number like 00 is sufficient, and on the other hand, the startup time is 1/10
0 at high speed, it is possible to provide a DC-DC converter with excellent current characteristics and excellent power start-up, which is particularly effective as a power source for terminal devices.
第１図は従来のDC−DCコンバータ、第２図は
第１図の動作波形図、第３図は本発明によるDC
−DCコンバータの基本構成図、第４図は第３図
の動作波形図、第５図は第３図に用いられる駆動
回路の一実施例回路図、第６図は第５図の動作波
形図である。
１１ａ，１１ｂ，１１ｃ……スイツチングトラ
ンジスタ、１２……電源、１３ａ，１３ｂ，１３
ｃ……トランス、１４ａ，１４ｂ，１４ｃ……ダ
イオード、１５……コンデンサ、２１……パルス
発振器、２３……1/3分周器、２４ａ……シフト
レジスタ、２５ａ……オア回路。
Figure 1 is a conventional DC-DC converter, Figure 2 is an operating waveform diagram of Figure 1, and Figure 3 is a DC-DC converter according to the present invention.
- Basic configuration diagram of the DC converter, Figure 4 is the operating waveform diagram of Figure 3, Figure 5 is an example circuit diagram of the drive circuit used in Figure 3, and Figure 6 is the operating waveform diagram of Figure 5. It is. 11a, 11b, 11c... Switching transistor, 12... Power supply, 13a, 13b, 13
c...Transformer, 14a, 14b, 14c...Diode, 15...Capacitor, 21...Pulse oscillator, 23...1/3 frequency divider, 24a...Shift register, 25a...OR circuit.
Claims (1)
路の導通・遮断により制御される複数の電圧伝送
形一方向駆動DC−DCコンバータ、 上記電圧伝送形一方向駆動DC−DCコンバータ
と同数の出力端子を有し、該各々の出力端子から
は、位置をずらせて１周期で１巡するパルス波形
を発生する駆動回路、 及び、それぞれ前記出力端子のうち一つが接続
され、入力されたパルス波形と、該入力されたパ
ルス波形を一定時間遅れで読み出し制御されるシ
フトレジスタの出力とをオア回路に入力し、該オ
ア回路の出力を前記スイツチ回路の駆動波形とし
て出力する複数の重ね合せ回路を備え、 各々の駆動波形の導通側は、時間的に隣接する
前後の駆動波形の導通側と重ね合うようになさし
め、各々の前記スイツチ回路を制御することを特
徴とする多相形DC−DCコンバータ。[Claims] 1. A plurality of voltage transmission type unidirectional drive DC-DC converters configured in parallel with diode-OR circuits and controlled by conduction/cutoff of a switch circuit, the same number as the voltage transmission type unidirectional drive DC-DC converters described above. a drive circuit that generates a pulse waveform that goes around once in one cycle by shifting its position from each output terminal, and one of the output terminals is connected to each output terminal to generate a pulse waveform that is inputted a plurality of superposition circuits that input the waveform and the output of a shift register that is controlled to read out the input pulse waveform with a certain time delay to an OR circuit, and output the output of the OR circuit as a driving waveform of the switch circuit; The conductive side of each drive waveform is made to overlap the conductive side of temporally adjacent preceding and succeeding drive waveforms to control each of the switch circuits. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56174564A JPS5879474A (en) | 1981-11-02 | 1981-11-02 | Dc/dc converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56174564A JPS5879474A (en) | 1981-11-02 | 1981-11-02 | Dc/dc converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5879474A JPS5879474A (en) | 1983-05-13 |
| JPH0250712B2 true JPH0250712B2 (en) | 1990-11-05 |
Family
ID=15980759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56174564A Granted JPS5879474A (en) | 1981-11-02 | 1981-11-02 | Dc/dc converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5879474A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2152770B (en) * | 1983-11-15 | 1987-04-29 | Yokogawa Hokushin Electric | Dc/dc converter |
| US4648020A (en) * | 1985-02-26 | 1987-03-03 | Vicor Corporation | Power booster switching at zero current |
| US4725768A (en) * | 1985-11-12 | 1988-02-16 | Toko Kabushiki Kaisha | Switching regulated power supply employing an elongated metallic conductive inductor having a magnetic thin film coating |
| US5019954A (en) * | 1989-06-23 | 1991-05-28 | Allied-Signal Inc. | AC/DC conversion with reduced supply waveform distortion |
| JPH03143261A (en) * | 1989-10-27 | 1991-06-18 | Koufu Nippon Denki Kk | Dc/dc converter |
| JP4957822B2 (en) * | 2010-03-19 | 2012-06-20 | サンケン電気株式会社 | Power supply |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51101824A (en) * | 1975-02-04 | 1976-09-08 | Jan Buaaderu Reinoto |
-
1981
- 1981-11-02 JP JP56174564A patent/JPS5879474A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51101824A (en) * | 1975-02-04 | 1976-09-08 | Jan Buaaderu Reinoto |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5879474A (en) | 1983-05-13 |
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