JPH03143261A - Dc/dc converter - Google Patents
Dc/dc converterInfo
- Publication number
- JPH03143261A JPH03143261A JP28101189A JP28101189A JPH03143261A JP H03143261 A JPH03143261 A JP H03143261A JP 28101189 A JP28101189 A JP 28101189A JP 28101189 A JP28101189 A JP 28101189A JP H03143261 A JPH03143261 A JP H03143261A
- Authority
- JP
- Japan
- Prior art keywords
- converters
- parallel
- input
- component
- reactors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 8
- 238000006243 chemical reaction Methods 0.000 claims description 20
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 7
- 230000010363 phase shift Effects 0.000 claims 1
- 230000001960 triggered effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 2
- 102220510630 APC membrane recruitment protein 1_Q14I_mutation Human genes 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＤＣ／ＤＣコンバータに関し、特にＤＣ／ＤＣ
変換回路を並列に接続して運転するＤＣ／ＤＣコンバー
タに関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a DC/DC converter, and particularly to a DC/DC converter.
This invention relates to a DC/DC converter that operates by connecting conversion circuits in parallel.
第３図は従来のＤＣ／ＤＣコンバータの一例を示すブロ
ック図である。FIG. 3 is a block diagram showing an example of a conventional DC/DC converter.
従来のＤＣ／ＤＣコンバータは、第３図に示すように、
複数のＤＣ／ＤＣ変換回路Ｑ、、、 Ｑ、２Ｑ １３．
Ｑ Ｉ ４１ Ｑ ＋ ｓを並列に接続して運転する
回路構成を有している。The conventional DC/DC converter, as shown in Figure 3,
Multiple DC/DC conversion circuits Q, Q, 2Q 13.
It has a circuit configuration in which Q I 41 Q + s are connected in parallel and operated.
第３図を参照すると、入力端子５１から直流電圧が入力
され、信号発生回路Ｚ２の出力端子６２にはトリガパル
スとして電圧信号Ｅｌｆが発生するので、電圧信号Ｅ、
に同期して、ＤＣ／ＤＣ変換回路Ｑ、、、Ｑ、、、Ｑ、
３．Ｑ、４．Ｑ、５が同時にスイッチングし、それぞれ
の入力端子５２と５３との間、５４と５５との間、５６
と５７との間、５８と５９との間、６０と６１との間に
それぞれ加わる直流電圧を、ＤＣ／ＤＣ変換回路ＱＩＩ
＋ Ｑ１２＋Ｑ ＋ ｓ 、 Ｑ ｌ ４ Ｉ Ｑ ｔ
ｓがそれぞれ電圧変換して出力端子６３に出力する。Referring to FIG. 3, a DC voltage is input from the input terminal 51, and a voltage signal Elf is generated as a trigger pulse at the output terminal 62 of the signal generation circuit Z2.
In synchronization with, the DC/DC conversion circuit Q,,,Q,,,Q,
3. Q, 4. Q and 5 switch simultaneously, between their respective input terminals 52 and 53, between 54 and 55, and between 56 and 56.
The DC voltages applied between and 57, 58 and 59, and 60 and 61 are applied to
+ Q12+Q + s, Q l 4 I Q t
s converts the voltage and outputs it to the output terminal 63.
第４図は第３図の各部の電圧及び電流の波形の−例を示
す信号波形図である。FIG. 4 is a signal waveform diagram showing examples of voltage and current waveforms at each part in FIG. 3.
信号発生回路Ｚ２から出力されるトリガパルスである第
４図（ａ）に示す電圧信号Ｅ１１によって、ＤＣ／ＤＣ
変換回路Ｑ、、、 Ｑ、２． Ｑ、３． Ｑ１４Ｉ Ｑ
ｌｓが動作し、それぞれの入力端子５２．５４．５６５
８．６０には、第４図（ｂ）、 （ｃ）、 （ｄ）、
（ｅ）、 （ｆ）にそれぞれ示す電流信号Ｉ ｌｌ＋
Ｉ １２． １１３＋ Ｉ １４１１ｔ５が得られ
る。DC/DC is controlled by the voltage signal E11 shown in FIG.
Conversion circuit Q, , Q, 2. Q, 3. Q14I Q
ls works, the respective input terminals 52.54.565
8.60, Figures 4(b), (c), (d),
Current signals Ill+ shown in (e) and (f), respectively
I 12. 113+I 1411t5 is obtained.
従って、ＤＣ／ＤＣ変換回路Ｑ、、・・・・・・Ｑｌ、
に流入する電流の総和は、電流信号Ｉ １１＋ 〜Ｌ、
の合成となり、第４図（ｇ）に示す電流信号Ｉｔｓとな
る。Therefore, the DC/DC conversion circuit Q,...Ql,
The sum of the currents flowing into is the current signal I 11+ ~L,
As a result, the current signal Its shown in FIG. 4(g) is obtained.
電流信号Ｉｃｅの実効値は、電流信号１１１＋ Ｉ
１２＋１１３１ １１４１ １ ＋ｓのそれぞれの実効
値の代数和である。The effective value of the current signal Ice is the current signal 111+I
It is the algebraic sum of the respective effective values of 12+1131 1141 1 +s.
なお、第３図のコンデンサＣｓ 、Ｃ６、Ｃ？ 。In addition, the capacitors Cs, C6, C? .
インダクタＬｓ 、 Ｌｓから戊る回路は、ローパス
型のノイズフィルタであり、上記の電流信号ＩＩ６の交
流分が、ノイズとして入力端子５１から電源側に伝わる
のを防いでいる。The circuit connected to the inductors Ls and Ls is a low-pass noise filter, and prevents the alternating current component of the current signal II6 from being transmitted as noise from the input terminal 51 to the power supply side.
上述した従来のＤＣ／ＤＣコンバータは、並列接続した
それぞれのＤＣ／ＤＣ変換回路が同一のタイミングで動
作するので、スイッチングノイズの基本波の周期がスイ
ッチング周波数に等しく、また、ノイズの振幅も大きい
ために、特にスイッチング周波数が充分に高くない場合
には、ノイズ断周波数を充分に低くするためのインダク
タに大型の物が必要になるという欠点を有している。In the conventional DC/DC converter described above, each DC/DC conversion circuit connected in parallel operates at the same timing, so the period of the fundamental wave of switching noise is equal to the switching frequency, and the amplitude of the noise is also large. Another drawback is that, especially when the switching frequency is not high enough, a large inductor is required to make the noise cutoff frequency sufficiently low.
本発明のＤＣ／ＤＣコンバータは、入力端子及び出力端
子の間でそれぞれ並列に接続して並列運転するＮ個のＤ
Ｃ／ＤＣ変換回路と、前記入力端子に並列に接続するコ
ンデンサと、一方を前記入力端子に直列に接続して他方
をＮ個の前記ＤＣ／ＤＣ変換回路に接続するインダクタ
と、Ｎ個の前記ＤＣ／ＤＣ変換回路のそれぞれにほぼ１
／Ｎずつ位相がずれたＮ個のトリガパルスのそれぞれを
与える信号発生回路とを有して構成されている。The DC/DC converter of the present invention has N Ds that are connected in parallel between an input terminal and an output terminal and operated in parallel.
a C/DC conversion circuit; a capacitor connected in parallel to the input terminal; an inductor, one of which is connected in series to the input terminal and the other connected to the N of the DC/DC conversion circuits; Approximately 1 for each DC/DC conversion circuit
and a signal generation circuit that provides each of N trigger pulses whose phases are shifted by /N.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明のＤＣ／ＤＣコンバータの一実施例を示
すブロック図である。FIG. 1 is a block diagram showing an embodiment of the DC/DC converter of the present invention.
第１図を参照すると、本実施例は、コンデンサＣ＋ 、
Ｃ２＋ Ｃ３、インダクタＬ、 、 Ｌ２ 、ＤＣ／
ＤＣ変換回路Ｑ、 、 Ｃ２，Ｃ３、Ｃ４，Ｃ５、ＤＣ
／ＤＣ変換回路のそれぞれにトリガパルスを与える信号
発生回路Ｚ１を備えて構成されている。Referring to FIG. 1, in this embodiment, capacitors C+,
C2+ C3, inductor L, , L2, DC/
DC conversion circuit Q, , C2, C3, C4, C5, DC
The signal generation circuit Z1 provides a trigger pulse to each of the /DC conversion circuits.
次に本実施例の動作について説明する。入力端子１１か
ら直流電圧が入力され、この直流電圧は、コンデンサＣ
＋ 、Ｃ２、Ｃｓ及びインダクタＬ１゜Ｌ２によって構
成されるノイズフィルタを通過し、ＤＣ／ＤＣ変換回路
Ｑ１．〜Ｑ、のそれぞれの入力端子１２．〜２１に加え
られる。そこで、ＤＣ／ＤＣ変換回路ＱＩ、〜Ｑ、は、
入力端子２２〜２６のそれぞれに信号発生回路Ｚ１から
供給されるトリガパルスに同期して動作し、それぞれの
入力端子１２．〜２１に加わる直流電圧を変換し５
て出力端子２７に出力する。Next, the operation of this embodiment will be explained. A DC voltage is input from the input terminal 11, and this DC voltage is applied to the capacitor C.
+, C2, Cs and the inductor L1°L2, and is then connected to the DC/DC conversion circuit Q1. ~Q, each input terminal 12. ~Added to 21. Therefore, the DC/DC conversion circuit QI, ~Q, is
It operates in synchronization with a trigger pulse supplied from the signal generation circuit Z1 to each of the input terminals 22 to 26, and the input terminals 12. The DC voltage applied to terminals 5 to 21 is converted and outputted to output terminal 27.
第２図は第１図の各部の電圧及び電流の波形の一例を示
す信号波形図である。FIG. 2 is a signal waveform diagram showing an example of voltage and current waveforms at each part of FIG. 1.
第２図（ａ）、 （ｂ）、 （ｃ）、 （ｄ）、 （ｅ
）のそれぞレニ示スヨうに、信号発生回路Ｚ１から出力
されるトリガパルスである電圧信号Ｅｌ 、 Ｅ２ 、
Ｅ、 、 Ｅ、 。Figure 2 (a), (b), (c), (d), (e
), the voltage signals El, E2, which are the trigger pulses output from the signal generation circuit Z1, respectively.
E, , E, .
Ｅ、は、それぞれの周期Ｔに対して互いにＴ１５ずつの
位相差を持ち、それぞれＤＣ／ＤＣ変換回゛路Ｑｌ 、
Ｃ２、Ｑｓ 、 Ｃ４、Ｑｓの入力端子２２゜２３．
２４，２５．２６に印加される。このため、電圧信号Ｅ
＋ 、Ｅ２ 、Ｅ３ 、Ｅ４ 、Ｅｓによってそれぞれ
ＤＣ／ＤＣ変換回路Ｑ、 、 Ｃ２，Ｃ３。E, have a phase difference of T15 with respect to each period T, and are respectively DC/DC conversion circuits Ql,
C2, Qs, C4, Qs input terminals 22°23.
24, 25, and 26. Therefore, the voltage signal E
+ , E2 , E3 , E4 and Es respectively form DC/DC conversion circuits Q, , C2 and C3.
Ｃ４，Ｑ、が動作し、それぞれの入力端子１２゜１４．
１６．１８．２０には、第２図（ｆ）、 （ｇ）、由）
（ｉ）、 （ｊ）に示す電流信号Ｉｌ＋ １２．Ｉ３
．１４゜工５が得られる。C4 and Q operate, and their respective input terminals 12°, 14.
On 16.18.20, Figure 2 (f), (g), Yu)
Current signal Il+ shown in (i) and (j) 12. I3
．． 14° work 5 is obtained.
従って、ＤＣ／ＤＣ変換回路Ｑ１．〜Ｑ、の入力電流の
総和は、１１．１２．１３．Ｉ４．Ｔ５の合成であり、
第２図１（ト）に示す電流信号Ｉ６となる。このため電
流信号Ｉ６の交流分の実効値は、６
電流信号Ｉ１．Ｉ２＋ Ｉ３＋ Ｉ４．ＩＳのそれ
ぞれの交流分の実効値にほぼ等しい程度であり、電流信
号■６の交流分の基本周波数は、それぞれの電流信号Ｉ
Ｉ、Ｉ２，１３．Ｉ４．Ｉｓの交流分の基本周波数の５
倍になっている。Therefore, the DC/DC conversion circuit Q1. The total input current of ~Q is 11.12.13. I4. It is a synthesis of T5,
The current signal I6 is shown in FIG. 1(G). Therefore, the effective value of the AC component of current signal I6 is 6. Current signal I1. I2+ I3+ I4. It is approximately equal to the effective value of each AC component of IS, and the fundamental frequency of AC component of current signal ■6 is equal to the effective value of each AC component of current signal I.
I, I2, 13. I4. 5 of the fundamental frequency of the AC component of Is
It's doubled.
なお、上記と同様に、Ｎ個のＤＣ／ＤＣＣｙ回路を並列
に運転する場合には、周期Ｔて互いにＴｉＮの位相差を
持ったＮ個のトリガパルスにより制御し、Ｎ個のＤＣ／
ＤＣＣｙ回路に流入する電流の総和の交流分を最小にし
、その交流分の基本波成分の周波数をＮ倍にすることが
できる。Similarly to the above, when N DC/DCCy circuits are operated in parallel, they are controlled by N trigger pulses with a period T and a phase difference of TiN, and the N DC/DCCy circuits are
It is possible to minimize the alternating current component of the total current flowing into the DCCy circuit and increase the frequency of the fundamental wave component of the alternating current component by N times.
以上説明したように、本発明のＤＣ／ＤＣＣｙバータは
、並列に運転されるそれぞれのＤＣ／ＤＣＣｙ回路の動
作タイミングをずらせて、ＤＣ／ＤＣＣｙ回路に流入す
る入力電流の総和の交流分を最小にするとともに、その
交流分の基本波成分を高周波化することにより、ノイズ
フィルタのしゃ断層波数を高く設定することが可能とな
り、ノイズフィルタのインダクタを小型化することがで
きるという効果を有している。As explained above, the DC/DCCy converter of the present invention shifts the operation timing of each DC/DCCy circuit operated in parallel to minimize the alternating current component of the total input current flowing into the DC/DCCy circuit. At the same time, by increasing the frequency of the fundamental wave component of the alternating current component, it is possible to set the blocking layer wave number of the noise filter to a high value, which has the effect of making it possible to downsize the inductor of the noise filter. .
第１図は本発明のＤＣ／ＤＣＣｙバータの一実施例を示
すブロク図、第２図は第１図の各部の電圧及び電流の波
形の一例を示す信号波形図、第３図は従来のＤＣ／ＤＣ
Ｃｙバータの一例を示すブロック図、第４図は第３図の
各部の電圧及び電流の波形の一例を示す信号波形図であ
る。
１１．１２．１３，１４．１５．１６．１？１８．１９
．２０．２１．２２，２３，２４゜２５．２６，５１．
５２，５３，５４，５５゜５６、 ５７． ５８． ５
９． ６０． ６１・・・・・・入力端子、２７．６２
．６３・・・・・・出力端子、Ｃ＋ 、Ｃ２゜Ｃｙ 、
Ｃｓ 、Ｃｓ 、Ｃｔ ・・・・・・コンデンサ、Ｅｌ
。
Ｅ２ 、Ｅ３． Ｅ＜ 、Ｅｓ 、Ｅｚ−・・’電圧信
号、１＋ 、Ｉｚ、Ｉ３，１４．Ｉｓ、Ｉｓ、Ｉｚ。
Ｉ １２１ Ｉ １３． Ｉ ＋４１ １１ｓ＋
Ｉ ｉｓ・・・・・・電流信号、ＬＩ Ｌ２．Ｌ
５．Ｌ６・・・・・・インダクタ、ＱＱ２ 、 Ｑ３．
Ｑ４ 、 Ｑｓ 、 Ｑ＋＋、 Ｑ＋２．Ｑ＋ｉ。
Ｑ１５・・・・・・ＤＣ／ＤＣＣｙ回路、２
・・・・・・信号発生回路。Fig. 1 is a block diagram showing an embodiment of the DC/DCCy converter of the present invention, Fig. 2 is a signal waveform diagram showing an example of voltage and current waveforms at each part of Fig. /DC
FIG. 4 is a block diagram showing an example of a Cy inverter, and FIG. 4 is a signal waveform diagram showing an example of voltage and current waveforms at each part in FIG. 11.12.13, 14.15.16.1?18.19
．． 20.21.22,23,24゜25.26,51.
52, 53, 54, 55°56, 57. 58. 5
9. 60. 61... Input terminal, 27.62
．． 63...Output terminal, C+, C2゜Cy,
Cs, Cs, Ct...Capacitor, El
. E2, E3. E<, Es, Ez-...'voltage signal, 1+, Iz, I3, 14. Is, Is, Iz. I 121 I 13. I +41 11s+
I is...Current signal, LI L2. L
5. L6...Inductor, QQ2, Q3.
Q4, Qs, Q++, Q+2. Q+i. Q15...DC/DCCy circuit, 2... Signal generation circuit.
Claims (1)
列運転するＮ個のＤＣ／ＤＣ変換回路と、前記入力端子
に並列に接続するコンデンサと、一方を前記入力端子に
直列に接続して他方をＮ個の前記ＤＣ／ＤＣ変換回路に
接続するインダクタと、Ｎ個の前記ＤＣ／ＤＣ変換回路
のそれぞれにほぼ１／Ｎずつ位相がずれたＮ個のトリガ
パルスのそれぞれを与える信号発生回路とを有すること
を特徴とするＤＣ／ＤＣコンバータ。N DC/DC conversion circuits connected in parallel between an input terminal and an output terminal and operated in parallel, a capacitor connected in parallel to the input terminal, and one connected in series to the input terminal and the other an inductor that connects the N DC/DC conversion circuits to the N DC/DC conversion circuits; and a signal generation circuit that provides each of the N trigger pulses with a phase shift of approximately 1/N to each of the N DC/DC conversion circuits. A DC/DC converter comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28101189A JPH03143261A (en) | 1989-10-27 | 1989-10-27 | Dc/dc converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28101189A JPH03143261A (en) | 1989-10-27 | 1989-10-27 | Dc/dc converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03143261A true JPH03143261A (en) | 1991-06-18 |
Family
ID=17633037
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28101189A Pending JPH03143261A (en) | 1989-10-27 | 1989-10-27 | Dc/dc converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03143261A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06133550A (en) * | 1992-10-12 | 1994-05-13 | Nemitsuku Ramuda Kk | Power supply |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5812573A (en) * | 1981-07-15 | 1983-01-24 | Hitachi Ltd | High frequency and high voltage power source circuit |
| JPS5879474A (en) * | 1981-11-02 | 1983-05-13 | Hitachi Ltd | Dc/dc converter |
| JPH01231661A (en) * | 1988-03-11 | 1989-09-14 | Fujitsu Ltd | Switching power supply |
-
1989
- 1989-10-27 JP JP28101189A patent/JPH03143261A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5812573A (en) * | 1981-07-15 | 1983-01-24 | Hitachi Ltd | High frequency and high voltage power source circuit |
| JPS5879474A (en) * | 1981-11-02 | 1983-05-13 | Hitachi Ltd | Dc/dc converter |
| JPH01231661A (en) * | 1988-03-11 | 1989-09-14 | Fujitsu Ltd | Switching power supply |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06133550A (en) * | 1992-10-12 | 1994-05-13 | Nemitsuku Ramuda Kk | Power supply |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100314358B1 (en) | Switch-Mode Power Supplies for Bridged Linear Amplifiers | |
| US5047910A (en) | Ideal sinusoidal voltage waveform synthesis control system | |
| US6828753B2 (en) | Input filter for A.C. motor phase current sensing | |
| JPS60156270A (en) | Drive controller of power converter | |
| JP2019527020A5 (en) | ||
| US4153930A (en) | Balanced control waveform for reducing inverter harmonics | |
| Fang et al. | Current mode Z-source inverter-fed ASD system | |
| US3767996A (en) | Low frequency multi-phase sinewave generator circuit | |
| CN112072943B (en) | H-bridge inverter power supply PWM modulation method for eliminating odd-order switch harmonic waves | |
| JPH06177651A (en) | Frequency synthesizer | |
| JPH03143261A (en) | Dc/dc converter | |
| RU2156539C2 (en) | Signal processing circuit, instrument for testing electric power consumption | |
| EP0159334A1 (en) | Pulse width modulated inverter | |
| JP5446804B2 (en) | Half-bridge power converter | |
| Ioannidis et al. | A novel uninterruptible power supply system with sinusoidal input-output characteristics and simplified control circuit | |
| CN112366971B (en) | Three-level inversion topological structure, control method thereof, single-phase and three-phase inversion circuit | |
| Nagalakshmi et al. | A single phase nine level inverter with reduced switches | |
| JPS61293170A (en) | Power converter | |
| JPH0496658A (en) | Inverter control system | |
| JPS61244106A (en) | Sine wave voltage generating circuit | |
| Ashraf et al. | Impedance Source Inverter with Maximum Gain | |
| Lim et al. | FPGA-based digital current mode controller for phase-shifted full-bridge PWM converter | |
| JPH06276678A (en) | Inverter circuit | |
| TW202332294A (en) | Rf band power supply device and pulse width modulation control method | |
| JPS5855756B2 (en) | AC power supply |