JPH0249299A - Memory - Google Patents

Abstract

PURPOSE:To improve the software efficiency of a program ROM and to simplify software and hardware by making an ordinary semiconductor RAM into a ROM in a circuit way and fixedly storing data in the RAM. CONSTITUTION:The gate of a P-channel FET1 and the drain of an N-channel FET4 are coupled, the drain of the FET1 and the gate of the FET4 are coupled, the gate of the FET1 is coupled to an earth, and the gate of the FET4 is coupled to supply VCC. Further, the gate of a P-channel FET3 and the drain of an N-channel FET2 are not coupled, and the drain of the FET3 and the gate of the FET2 are not coupled. Since the gate of the FET1 goes to ground potential here, the FET1 always goes to an ON-state, and an (a) point goes to 'H'. Further, since the gate of the FET4 goes to the potential of the supply VCC, the FET4 always goes to the ON-state, and a (b) point always goes to 'L'. Consequently, whenever the supply VCC is supplied, the (a) point goes to 'H', and the (b) point goes to 'L' respectively without any conditions, and this state can be read from a data line Mi and the inverse of Mi.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor memory device, and is used, for example, in a microcomputer for small electronic equipment.

<Prior Art> When data that does not need to be rewritten is stored in a microcomputer as a database, conventionally the data code is written in a ROM that stores a program using machine language instructions. In addition, since scientific calculators handle large amounts of data such as built-in functions, the program RO
R for data enables pattern ordering more efficiently than M
I was writing the data code to OM. Figure 4 shows the system configuration of this scientific calculator.
A data ROM 12 is provided separately from II.

<Problems to be Solved by the Invention> As mentioned above, conventionally, data has been fixedly stored in a program ROM or a dedicated ROM.
This method has disadvantages in that the software is inefficient and the original processing program is overwhelmed by data. In addition, in the case of using a dedicated data ROM, the software efficiency is good, but since it has dedicated addresses and instructions, it is undesirable in terms of hardware, for example, in terms of chip area.
Since the data ROM has a limited capacity, it has the disadvantage of being inefficient and lacking in flexibility if used improperly.

The present invention has been made in view of the above circumstances, and its purpose is to improve RAM by converting RAM into ROM in circuit form.
To provide a memory device that can permanently store data in M.

<Means for Solving the Problems> In order to achieve the above object, in the memory device according to the present invention, the gate of the P-channel FETI and the drain of the N-channel FET4 are coupled, and the P-channel FETI is connected to the drain of the N-channel FET4.
The drain of T+ and the gate of N-channel FET 4 are coupled, the gate of P-channel FETI is coupled to ground, the gate of N-channel FET 4 is coupled to the power supply, and the gate of P-channel FET 3 and the drain of N-channel FET 2 are not coupled. It has a structure in which the drain of P-channel FET 3 and the gate of N-channel FET 2 are not coupled.

<Function> RAM is originally a writable/readable memory, but in the present invention, in the circuit creation process of the semiconductor RAM, the circuit is converted into a ROM and data is fixedly stored.

That is, in the drain-gate coupled flip-flop circuit, P-channel FET3 and N-channel FE
Breaking the drain-gate coupling with T2, the P-channel F
Connect the gate of ET+ to ground and create an N-channel FET.
By coupling the gate of FET 4 to a power supply, the drain of P-channel FET I is held at 1'' and the drain of N-channel FET 4 is held at 0.

<Embodiment> FIG. 1 shows the circuit configuration of a memory cell (1 bit) in a memory device of this embodiment. In the figure, 1 and 3 are P-channel FETs; 2. 4. 5.6 is an N-channel FET, M, , M are data lines, and xj, yi are address lines.

In this circuit, the gate of P-channel FETI and the drain of N-channel FET4 are coupled, and P-channel FETI is connected to the drain of N-channel FET4.
The drain of TI is coupled to the gate of N-channel FET 4, the gate of P-channel FETI is coupled to ground, and the gate of N-channel FET 4 is coupled to power supply Vcc. Furthermore, the gate of P channel FET3 and N
The drain of channel FET2 is non-coupled, and the drain of P-channel FET3 and the gate of N-channel FET2 are non-coupled.

This circuit breaks the drain-gate coupling between P-channel FET 3 and N-channel FET 2, couples the gate of P-channel FET I to ground, and connects the gate of N-channel FET 4 to the power supply in the normal semiconductor RAM shown in FIG. ■ Combines with Ce. That is, to create this circuit, as shown in Figure 3, cut the wires B and D,
Wirings A and C shown by broken lines are formed.

First, the storage operation in the normal RAM shown in FIG. 2 will be explained. Due to this memory cell addressing, address lines x and yi both go to "H" level, then data line Mt goes to "H" level, and Mt goes to "H" level.
, becomes "L" level, point a is "H", P channel FET3 is off, N channel FET4 is on, point b is "L", P channel FETI is on, N channel F
ET2 is turned off. As a result, the potential of the power supply V ce is supplied to the gates of P-channel FET3 and N-channel FET4, and the ground potential is supplied to the gates of P-channel FET3 and N-channel FET4.
The signal is supplied to the gate of the channel FET 2, and the point a is stabilized at the "H" level and the point b is stabilized at the "L" level. To read data, address lines XJ and Y+ are set to "H" level, and data line Mi is read.

Read the voltage level of M.

The operation of the circuit according to the present invention shown in FIG. 1 will be explained. Since the gate of the P-channel FETI is at ground potential, the P-channel FETI is always on, and the point a is always at the "H" level.

Furthermore, since the gate of the N-channel FET4 is at the potential of the power supply Vcc, the N-channel FET4 is always on, and the point b is always at the "L" level.

That is, each time the power supply VCC is supplied, the point a becomes 'H' and the point b becomes L' unconditionally, and this state can be read from the data line M82M.

In manufacturing the semiconductor RAM of the present invention, all wiring cutting and connection processes are performed on a metal mask and a diffusion mask. This can be done without adding a new mask or process by inputting the ROMization information into mask data of a normal semiconductor RAM using CAD.

<Effects of the Invention> As explained above, in the present invention, a normal semiconductor RAM can be converted into a ROM by simple circuit modification. It is possible to eliminate the need for a conventional program that generates a code from a ROM and writes the data code to a RAM using software, thereby improving the software efficiency of the program ROM. Furthermore, since a dedicated data ROM can be eliminated, the hardware and software can be simplified.

[Brief explanation of the drawing]

1 is a diagram showing a circuit configuration of an embodiment of the present invention, FIG. 2 is a diagram showing a circuit configuration of a semiconductor RAM, FIG. 3 is a diagram illustrating a method of manufacturing a memory device according to an embodiment of the present invention, and FIG. 1 is a diagram showing the system configuration of a scientific calculator. 1.3...P channel FET 2.4...N channel FET XJ, Y,...address line M,,M,...data line

Claims (1)

[Claims] P-channel FET1 gate and N-channel FET
The drain of P-channel FET1 is coupled to the gate of N-channel FET4, the gate of P-channel FET1 is coupled to ground, the gate of N-channel FET4 is coupled to the power supply, and the drain of P-channel FET1 is coupled to the gate of N-channel FET4.
A memory device characterized by a structure in which the gate of ET3 and the drain of N-channel FET2 are non-coupled, and the drain of P-channel FET3 and the gate of N-channel FET2 are non-coupled.