JPH0248144B2 - HANDOTAISHUSEKIKAIRO - Google Patents
HANDOTAISHUSEKIKAIROInfo
- Publication number
- JPH0248144B2 JPH0248144B2 JP14468684A JP14468684A JPH0248144B2 JP H0248144 B2 JPH0248144 B2 JP H0248144B2 JP 14468684 A JP14468684 A JP 14468684A JP 14468684 A JP14468684 A JP 14468684A JP H0248144 B2 JPH0248144 B2 JP H0248144B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- semiconductor integrated
- power supply
- input
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000001681 protective effect Effects 0.000 claims description 2
- 230000006378 damage Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体集積回路、特に入力保護回路を
備えた半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit equipped with an input protection circuit.
半導体集積回路において、静電破壊対策の面か
ら、入出力保護ダイオードや入出力保護抵抗を介
して内部回路素子に接続する場合が非常に多い。
このような場合、通常スクライブ線と電源ライン
の間のパツド周辺に、保護ダイオードや内部素子
を配置して製造することが一般によく行われてい
る。
Semiconductor integrated circuits are often connected to internal circuit elements via input/output protection diodes or input/output protection resistors to prevent electrostatic damage.
In such cases, it is common practice to place protection diodes and internal elements around the pad between the scribe line and the power supply line.
ところが入出力端子に、外部から加わつた静電
パルスは、ダイオードを通して電源へ放電しよう
とするため、その経路内に内部素子が存在すると
ゲート破壊を起こす可能性がある。 However, an electrostatic pulse applied to the input/output terminal from the outside tends to discharge to the power supply through the diode, so if an internal element is present in the path, gate destruction may occur.
例えば従来の集積回路においては第１図に示す
ように、入出力端子２に接続されている入力保護
ダイオード（Ｎ型…５，Ｐ型…８）、入力保護抵
抗９、内部素子のゲート７、ソース１０、コンタ
クト６，６ａ，６ｂ，６ｃは、スクライブ線１と
電源ライン（４ａはVdd、４ｂはVss）の間の領
域に配されている。この時、パツド２からの静電
パルスは、引き出しアルミ３を通り、ダイオード
８を通して、電源ライン上のコンタクト６ｃから
電源４ａへ放電しようとする。しかしその時、放
電経路６ａから６ｃの間に、ゲート、ドレインコ
ンタクトがあるため、ゲート破壊を起す可能性が
ある。 For example, in a conventional integrated circuit, as shown in FIG. The source 10 and the contacts 6, 6a, 6b, and 6c are arranged in a region between the scribe line 1 and the power supply line (4a is Vdd, 4b is Vss). At this time, the electrostatic pulse from the pad 2 passes through the lead aluminum 3, passes through the diode 8, and attempts to discharge from the contact 6c on the power supply line to the power supply 4a. However, at that time, since there are gate and drain contacts between the discharge paths 6a and 6c, there is a possibility that the gate will be destroyed.
本発明は上記従来例の欠点に鑑み提案されたも
のであり、入・出力端子に接続される保護ダイオ
ードと同じ入・出力端子に接続される内部回路素
子とを電源ラインに関して分離配置することによ
り、静電破壊に強い半導体集積回路の提供を目的
とする。
The present invention has been proposed in view of the drawbacks of the above-mentioned conventional examples, and by arranging protection diodes connected to input/output terminals and internal circuit elements connected to the same input/output terminals separately with respect to the power supply line. The aim is to provide semiconductor integrated circuits that are resistant to electrostatic damage.
本発明は保護ダイオードと内部回路素子に接続
される入・出力端子を有する半導体集積回路にお
いて、電源ラインを中心に、前記端子側に同端子
と接続される前記保護ダイオードを配置し、電源
ラインを中心に前記端子側と反対側に同端子に接
続される内部回路素子を配置することを特徴とす
る。
The present invention provides a semiconductor integrated circuit having a protection diode and an input/output terminal connected to an internal circuit element, in which the protection diode connected to the terminal is placed on the terminal side with the power line at the center, and the power line is connected to the power line. The device is characterized in that an internal circuit element connected to the terminal is disposed at the center on a side opposite to the terminal.
以下図面を参照して本発明の実施例を説明す
る。第２図は本発明の実施例に係る半導体集積回
路のパターン配置図であり、第１図と同じ番号は
同じ素子を示す。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a pattern layout diagram of a semiconductor integrated circuit according to an embodiment of the present invention, and the same numbers as in FIG. 1 indicate the same elements.
実施例においては図示するように、入出力端子
に接続される内部回路素子７を電源ライン４ａに
対してパツド２の反対側に配置している。従つて
パツド２に静電パルスが印加したとき、このエネ
ルギーはダイオード８からコンタクト６ｃを介し
て電源ライン４ａに吸収される。この場合、ダイ
オード８から電源ライン４ａへの放電経路中に回
路素子が存在しないのでゲート破壊を起すことも
ない。 In the embodiment, as shown in the figure, the internal circuit element 7 connected to the input/output terminal is arranged on the opposite side of the pad 2 with respect to the power supply line 4a. Therefore, when an electrostatic pulse is applied to pad 2, this energy is absorbed from diode 8 to power supply line 4a via contact 6c. In this case, since there are no circuit elements in the discharge path from the diode 8 to the power supply line 4a, gate breakdown will not occur.
以上説明したように本発明によれば、端子に加
つた静電パルスが電源ラインへ放電するとき、そ
の経路に回路素子のゲートが存在しないので、静
電破壊に強い半導体集積回路が得られる。
As described above, according to the present invention, when an electrostatic pulse applied to a terminal is discharged to a power supply line, there is no gate of a circuit element in the path, so a semiconductor integrated circuit that is resistant to electrostatic damage can be obtained.
第１図は従来例に係る集積回路パターン図であ
り、第２図は本発明の実施例に係る集積回路パタ
ーン図である。
１……スクライブ線、２……ボンデイングパツ
ド、３……パツドからの引出しアルミ、４ａ，４
ｂ……電源ライン、５……Ｎチヤンネル型ダイオ
ード、６，６ａ，６ｂ，６ｃ……コンタクト、７
……ゲート、８……Ｐチヤンネル型ダイオード、
９……保護抵抗、１０……ソース。
FIG. 1 is an integrated circuit pattern diagram according to a conventional example, and FIG. 2 is an integrated circuit pattern diagram according to an embodiment of the present invention. 1...Scribe wire, 2...Bonding pad, 3...Aluminum drawn out from pad, 4a, 4
b...Power line, 5...N-channel diode, 6, 6a, 6b, 6c...Contact, 7
...gate, 8...P channel type diode,
9...protective resistance, 10...source.
Claims (1)
入・出力端子を有する半導体集積回路において、
電源ラインを中心に前記端子側に同端子と接続さ
れる前記保護ダイオードを配置し、電源ラインを
中心に前記端子側と反対側に同端子に接続される
内部回路素子を配置することを特徴とする半導体
集積回路。1. In a semiconductor integrated circuit having input/output terminals connected to protection diodes and internal circuit elements,
The protective diode connected to the terminal is arranged on the terminal side with the power line at the center, and the internal circuit element connected to the terminal is arranged on the opposite side of the terminal with the power line at the center. semiconductor integrated circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14468684A JPH0248144B2 (en) | 1984-07-12 | 1984-07-12 | HANDOTAISHUSEKIKAIRO |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14468684A JPH0248144B2 (en) | 1984-07-12 | 1984-07-12 | HANDOTAISHUSEKIKAIRO |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6123357A JPS6123357A (en) | 1986-01-31 |
| JPH0248144B2 true JPH0248144B2 (en) | 1990-10-24 |
Family
ID=15367897
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14468684A Expired - Lifetime JPH0248144B2 (en) | 1984-07-12 | 1984-07-12 | HANDOTAISHUSEKIKAIRO |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0248144B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE465664B (en) * | 1990-02-09 | 1991-10-14 | Philips Norden Ab | DEVICE FOR RECORDING AND / OR READING INFORMATION |
-
1984
- 1984-07-12 JP JP14468684A patent/JPH0248144B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6123357A (en) | 1986-01-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR0134285B1 (en) | Protection circuit for protecting a semiconductor device from a voltage surge | |
| JP3147849B2 (en) | Protection circuit for semiconductor integrated circuit device | |
| KR980006220A (en) | Semiconductor device with static electricity protection circuit | |
| JPH08181219A (en) | Semiconductor integrated circuit device | |
| JPH0248144B2 (en) | HANDOTAISHUSEKIKAIRO | |
| JPH0685174A (en) | Semiconductor integrated circuit device | |
| JPH0766370A (en) | Semiconductor device | |
| JPH0228266B2 (en) | ||
| JPS6221018Y2 (en) | ||
| JPH0590520A (en) | Semiconductor protective device | |
| JP3692186B2 (en) | Semiconductor device | |
| JPH07235604A (en) | Semiconductor device | |
| JPH03248567A (en) | Transistor for protecting input | |
| JP3271435B2 (en) | Semiconductor integrated circuit device | |
| JP3134443B2 (en) | Semiconductor input protection device | |
| JP2000269440A (en) | Esd protection circuit | |
| JPS63291470A (en) | Protective circuit for semiconductor integrated circuit device | |
| JPS62165353A (en) | Semiconductor integrated circuit device | |
| JPH04354158A (en) | Semiconductor element | |
| JPS6251231A (en) | Semiconductor integrated circuit device | |
| JP2878765B2 (en) | Semiconductor device | |
| JP2003133422A (en) | Input protection circuit | |
| JPH0314233B2 (en) | ||
| JPH04199865A (en) | Semiconductor device | |
| JPS63229857A (en) | Protective circuit against electrostatic breakdown |