JPH0247914A - Digital noise elimination system - Google Patents

Abstract

PURPOSE:To attain the flexible consecution time of elimination object noise without losing the miniaturization and economy by selecting a storage signal this time or a preceding stored output signal in response to the result of recent comparison of digital signals at a prescribed number of times. CONSTITUTION:Recent digital input signals di coming m-times or the like are stored in plural-set (e.g., m) of 1st storage means 100, they are compared by a comparison means 200 and a selection means 400 is controlled in response to the result of comparison. Then when they are all coincident, the storage content of the means 100 is outputted, and if they are dissident, the preceding output stored in the 2nd storage means 300 is outputted. Thus, momentary noise is eliminated without adding a parity bit to the digital signal and the consecutive time of momentary noise being an object of elimination is adjusted easily and flexibly without losing the miniaturization and the economy.

Description

[Detailed description of the invention] [Summary! Regarding the improvement of a digital noise cancellation method that makes it possible to cancel noise from digital signals, we have realized a digital noise cancellation method that does not impair the miniaturization and economicization of digital communication systems (and can flexibly adjust the duration of the noise to be canceled). A first accumulating means for accumulating the digital input signal that arrived most recently at a predetermined time among the digital input signals arriving in time series; A comparison means for comparing the input signals with each other, a second accumulation means for accumulating the output digital output signals, and a first accumulation means when the digital input signals of the predetermined times compared by the comparison means all match. The means selects a digital input signal to be accumulated, and when the digital input signals of the predetermined times compared by the comparing means do not match, the second accumulating means selects the previous digital output signal to be accumulated, and selects the previous digital output signal to be accumulated as the digital output signal. The configuration is such that a selection means for outputting is provided.

[Industrial application field]

The present invention relates to an improvement in a digital noise cancellation method that makes it possible to cancel noise from a digital signal.

For example, in a digital communication system that transmits a digital signal consisting of - or multiple bits, if any bit of the digital signal is erroneously transmitted due to instantaneous noise etc., it will cause a malfunction in the digital communication device. .

Therefore, it is important to eliminate noise from the transmitted digital signal.

[Conventional technology]

FIG. 4 is a diagram showing an example of a conventional digital noise cancellation method.

Conventionally, as a noise cancellation method for analog signals, for example, low-pass filters have been widely used.
Instantaneous noise was eliminated by passing the transmitted analog signal through a low-pass filter or the like.

On the other hand, as a noise cancellation method for digital signals, for example, as shown in FIG. By inputting the digital signal d to be transmitted to the receiving side to the parity generation circuit 1-1, a digital signal d with a parity bit is generated and transmitted to the receiving side. It is widely practiced to input the digital signal dp with a parity bit into the parity check circuit 1-2 to detect the presence or absence of an error and to restore the error-free digital signal d.

[Problem to be solved by the invention]

As is clear from the above explanation, in conventional digital noise cancellation methods, the transmitting side adds parity bits and 7 bits to the digital signal to be transmitted, and the receiving side checks the digital signal with parity bits for errors. Although it is widely practiced to
-1, it is necessary to provide a parity check circuit 1-2 on the receiving side, which not only impairs the miniaturization and economicalization of the digital communication system, but also impairs the composition of the digital signal and the duration of the instantaneous noise to be eliminated. There was a risk that the relationship would be limited.

An object of the present invention is to realize a digital noise cancellation method that can flexibly adjust the duration of noise to be canceled without impairing the miniaturization and economicization of a digital communication system.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 100 is a first storage means provided according to the present invention, 200 is a comparison means provided according to the present invention, 300 is a second storage means provided according to the present invention, and 400 is a 1 is a selection means provided according to the invention.

[Effect]

The first storage means 100 stores the most recently arrived digital input signal d of the digital input signals d, which arrive in chronological order.

The comparison means 200 mutually compares a predetermined number of digital input signals d stored in the first storage means 100.

The second storage means 300 stores the previously output digital output signal d0.

The selection means 400 selects the digital input signal d to be accumulated by the first accumulation means 100 when all the digital input signals d of the predetermined times compared by the comparison means 200 match. If the predetermined digital input signals d do not match, the second storage means 300 selects the previous digital output signal d0 stored and outputs it as the digital output signal d0.

As a result of the above, instantaneous noise having a duration that is less than the arrival interval of the digital input signal d, which is the number of digital input signals that can be stored by the first storage means 100, is erased from the digital output signal d0. .

Furthermore, by adjusting the number of digital input signals accumulated by the first accumulation means 100, the duration of instantaneous noise to be eliminated from the digital output signal can also be easily adjusted.

Therefore, instantaneous noise can be canceled without adding parity bits or the like to the digital signal, and the duration of the instantaneous noise to be canceled can be easily adjusted, making the digital communication system more compact and economical. and promote flexibility.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a digital noise cancellation method according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating input/output signal waveforms in FIG. 2.

In FIG. 2, the first storage means 10 in FIG.
0, a distribution circuit 2 and eight memories 3 (individual memories 3 are referred to as 3-1 to 3-8, hereinafter the same) are provided, and a comparator 4 is provided as the comparison means 200 in FIG. Second storage means 30 in Figure 1
A memory 6 is provided as 0, and a selector 5 is provided as selection means 400 in FIG.

In FIGS. 2 and 3, when the digital input signal d, consisting of one bit, arrives at the distribution circuit 2 in time series at a constant interval τ, the distribution circuit 2 receives the first digital input signal d8. (However, n in dl indicates the order of arrival)
are delivered and stored in the memory 3-1, the digital input signals a and Z that arrived second are delivered and stored in the memory 3-2, and in the same manner, the digital input signal d1 that arrived at the eighth exit is
is delivered and stored in the memory 3-8.

Further, the digital input signal di9 that has arrived at the ninth exit is delivered and stored in the memory 3-1 again, and the digital input signal a=+ that was initially stored in the memory 3-1 is deleted.

As a result, the memories 3-1 to 3-8 always contain the eight digital input signals dill to d that arrived the last six times.
0.7 will be accumulated.

Furthermore, the digital output signal d021 output from the selector 5 is stored in the memory 6.

Further, the contents stored in the memory 3-8 and the contents stored in the memory 6 are input to the selector 5.

Further, the comparator 4 receives the digital input signals dia to d iy++ stored in the memories 3-1 to 3-8.
? Compare the logical values of all digital input signals dl to dimp? When the logical values of d ink? match, the selector 5 selects the stored content of the memory 3-8 and outputs it as the digital output signal d (Ilk), and the logical values of the digital input signals d is to d ink? However, if they do not match, the selector 5 selects the content stored in the memory 6 and outputs it as a digital output signal d.7.

Therefore, for example, the digital input signal di in FIG.
In the state where l to d, 11 are stored in the memories 3-1 to 3-8, the digital input signals dil to a=S and dill are logic "0", and the digital input signal a=
4 to di? is the logic "1", the comparator 4 selects the stored contents of the memory 6 (for example, logic "0") to the selector 5.
to select the digital output signal aOS (=logic “O”).
) and store logic "0" in the memory 6.

In the same way, until the digital input signal d419 arrives, the stored contents of the memories 3-1 to 3-8 will not all become logic "0" or logic "1".
The comparator 4 causes the selector 5 to select the stored contents of the memory 6 (logic "0") for 4 m consecutively, and the digital input signal dos is set to logic "0".

Next is the digital input signal atZ. When the signals d, 1 . d1° is accumulated and stored in memories 3-1 to 3-
Since the stored contents of memories 3-8 are all logic "1", the comparator 4 sends the selector 5 to the stored contents of memories 3-8 (= logic "1").
”) is output as a digital output signal doto, and the logic “1” is stored in the memory 6.

Thereafter, digital input signals d, 2. Even when the following data arrives at the distribution circuit 2, the stored contents of the memories 3-1 to 3-8 are all logic "1", so the comparator 4 continues to select the stored contents of the memory 3-8 to the selector 5. and digital output signal d. In addition to outputting as fi, memory 6
Accumulate in.

As is clear from the above description (according to this embodiment, unless the digital input signal dia continues to have the same logical value at intervals of Since d is continuously outputted, instantaneous noise of less than the interval (8τ) superimposed on the digital input signal d is canceled from the digital output signal d.

Note that FIGS. 2 and 3 are only one embodiment of the present invention, and the number of memories 3 is not limited to eight, for example. Although various modifications may be considered depending on the duration of the instantaneous noise, the effect of the present invention remains the same in either case.

Further, the number of focuses of the digital input signal dia is not limited to one bit, and many other modifications may be considered, but the effects of the present invention remain the same in any case.

〔Effect of the invention〕

As described above, according to the present invention, instantaneous noise can be canceled without adding parity bits etc. to a digital signal, and the m duration of the instantaneous noise to be canceled can be easily adjusted. This will promote the miniaturization, economy, and flexibility of communication systems.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a digital noise cancellation method according to an embodiment of the present invention, FIG. 3 is a diagram illustrating input/output signal waveforms in FIG. 2, and FIG. The figure shows an example of a conventional digital noise cancellation method. In the figure, -1 is a parity generation circuit, 1-2 is a parity check circuit, 2 is a distribution circuit, 3 and 6 are memories, 4
is a comparator, 5 is a selector, 100 is a first storage means, 200 is a comparison means, 300 is a second storage means, 40
0 indicates the selection means, Mitsuaki 0 Torarizu i l Figure n = 123tJ5, 7Fl wo 10 /11213 /
411! ;/l/7#'120212223211'$
Z diagram 1 ke 1 to input/output I word name J 'if 3 diagram

Claims (1)

[Claims] Digital input signals (d_i) arriving in time series,
The digital input signal (d_i
); a comparison means (200) for mutually comparing the predetermined digital input signals (d_i) accumulated in the first accumulation means (100); When the second accumulating means (300) for accumulating the output digital output signal (d_o) and the digital input signal (d_i) of the predetermined times compared by the comparing means (200) all match, The first storage means (100) selects the digital input signal (d_i) to be stored, and when the digital input signals (d_i) of the predetermined times compared by the comparison means (200) do not match, the second storage means (100) selects the digital input signal (d_i) to be stored. selection means (400) for selecting the previous digital output signal (d_o) accumulated by the means (300) and outputting it as a digital output signal (d_o);
) A digital noise cancellation method.