JPH0245939A - Schottky barrier type field effect transistor - Google Patents

Abstract

PURPOSE:To prevent increase of series resistance constituents from a drain electrode io a source electrode by providing a gate electrode with an insulation film at the side wall on an active layer and providing a high-concentration layer at the same depth as the active layer being adjacent to the active layer and the side wall. CONSTITUTION:An active layer 2 is formed by implanting Si<+> ion of a GaAs substrate 1 and the active layer 2 is activated by annealing. A gate electrode 3 is formed on the active layer 2 and an insulation film 4 is formed over the entire surface. A photoresist 5 is formed on the substrate 1 other than the area on the active layer 2 and the insulation film 4 is eliminated by the RIE method to allow a side wall 4a of insulation film to remain at the side part of the gate electrode 3. The active layer 2 is etched away with the photoresist 5, the gate electrode 3, and the side wall 4a as masks and the photoresist 5 is eliminated. Then, a high-concentration layer 6 is allowed to grow being adjacent to the active layer 2 and the side wall 4.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a Schottky barrier field effect transistor, and more particularly to a Schottky barrier field effect transistor free of short channel effects.

(b) Conventional technology In general, Schottky barrier field effect transistor CME
SFET) has a problem in that as the gate length is shortened, a leakage current flows into a high resistance layer provided below the active layer, which is the so-called short channel effect.

Therefore, as a structure that can eliminate this short channel effect, as shown in Fig. 4, a self-line f
In selective growth structures have been proposed (e.g., In
t, Symp, GaAs and Re1ated
Compounds, Japan, 1985 F2O
See 5-510. ).

In this structure, a N-pole is formed on the active layer formed by ion implantation, and the gate is self-aligned using an insulating film formed on the side of the gate electrode. Electrode-
This can be obtained by selectively forming a high concentration layer on the surface of the semiconductor substrate 1411 adjacent to the semiconductor substrate 1411 using a metal organic chemical vapor deposition (MOCVD) method or the like.

(c) Problems to be Solved by the Invention However, in the above-described structure, a problem arises in that the series resistance component increases due to the long current path from the drain electrode to the source electrode (b).

The present invention has been made in view of the above-mentioned circumstances, and aims to provide a Schottky barrier FJ [field effect transistor] which eliminates the short channel effect but does not increase the series resistance component.

B) Means for Solving the Problems The present invention comprises an active layer formed on a semi-insulating substrate, a gate tl electrode provided on the active layer, and a gate tl electrode formed on both sides of the gate electrode and on the active layer. a side wall made of an insulating film;
A high 1 degree layer adjacent to the active layer and the side wall and formed at substantially the same depth as the active layer, and an ohmic electrode provided on the high 1 degree layer. and the game provided on this active layer)! and a high concentration layer made of a heat-resistant ohmic metal and an ohmic region, which is formed adjacent to the active layer and at approximately the same depth as the active layer. It is a field effect transistor.

(E) Effect According to the present invention, the high concentration layer is formed at approximately the same depth as the active layer, so there is no short channel effect, and the high concentration layer is formed adjacent to the active layer. series resistance is small.

(f) Example A manufacturing method of an example of the present invention is shown in FIGS. 1(a) to (1).
The explanation will be based on K.

Semi-insulating GaAs substrate (11 implanted ions s t'; implantation energy 40KeV, implantation f5 x 10"cc
Ion implantation is performed under the conditions of -' to selectively form an active layer (2) with a thickness of 500 to 700X. Next, annealing (850°C,
5 seconds) to activate the active layer (2) (see Figure 1(a)
)).

A gate electrode (31) made of a high melting point metal such as W8i and having a gate length of 4 μm is formed on the active layer (2), and then an insulating film (4) such as SiOW is formed on the entire surface by plasma CVD method or the like (first Figure (b]).

Active layer (substrate other than 21 (7 photoresist on 11)
5) is formed, and the insulating film (4) is removed by RIE method (@1 (C)). Then, a side wall (4a) of @α2 μm is formed on the side of the gate electrode (31).

Photoresist (5), gate electrode (3) and Il! i
Using the I wall (4a) as a mask, the active layer (2) is etched by BCR plasma CVD method or the like, and the etched portion (
8). After that, the photoresist (51) is removed and the surface is cleaned with HC/etc. (Fig. 1(d))
.

High 1sr on the etching part (8) by MOCVD method etc.
ate++ approx. 1s o o Xa length < v, 1
Figure (e)>.

At this time, by placing the high concentration layer (6) adjacent not only to the active layer (2) but also to the side wall (4a), the thickness necessary for ohmic contact can be obtained.

Finally, an ohmic electrode (7) made of Au, Ni, Au+Qe, etc. is formed on the high concentration layer (6), and the ohmic electrode +71 is alloyed (as shown in FIG. 1).

The MES FET fabricated by the above-mentioned method has a high concentration layer (
There is no protruding portion below the active layer (2) of 6), and the high concentration layer (6) has a structure that is continuous with the active layer +21 in the lateral direction.

Next, a manufacturing method of another embodiment of the present invention will be explained based on FIGS. 2(a) to (e).

Semi-insulating GaAs substrate (111 implanted ions Si”,
Injection x channel df -40Key, injection amount s x 1o
Ion implantation was performed under 12ts-'o conditions, and the thickness was 5oO~70
0X active layer α2 is selectively formed (FIG. 2(a))
.

A gate electrode u3 made of a high-melting point metal such as WSi and having a gate length α4 μm is formed on the active layer tiz, and then an insulating film (2) of SiO2 or the like is formed on the entire surface by plasma CVD or the like (see FIG. 2).

7 otres resists on the substrate αD other than on the active layer a3
is formed, and the insulating film (14) is removed (by RIE method).
Figure 2 (C)). Then, a width α is formed on the side of the gate electrode αJ.
A lateral wall (14a) of 2μ disease is formed.

Using the photoresist (151, gate electrode flat and sidewalls (141) as a mask, the active layer (121) is etched by ECR plasma RIB method, etc., and etching [18
1, then remove the photoresist (t51,
The surface is cleaned with HC/etc. (FIG. 2(d)). The etching depth at this time is also slightly shallower than the depth of the active layer α2.

W, Mo, In, Ge or W on the etching part tt8
A heat-resistant ohmic metal aη such as Ni, NiI2, Ni, etc. is formed, followed by cyannealing (850°C, 5 seconds) using a cap annealing method using a SiN film to activate the active layer α2 and form a heat-resistant ohmic electrode. (1g
Figure 2 (C)). This heat-resistant ohmic metal a″71 is 80
It is a metal whose contact resistance does not increase even when subjected to high-temperature heat treatment of 0"C or more.The ohmic region (1!) formed by alloying the heat-resistant oak building metal aη approximately corresponds to the depth of the active layer (121), and The high concentration layer αG is composed of a heat-resistant ohmic electrode (lF3) and an ohmic region σ9.

In this actual case, the heat-resistant ohmic metal an was formed to protrude beyond the substrate surface, but it may be formed flush with the Makukai II surface or below the substrate u1 surface, in which case the sidewall There is no need to form (14a).

In addition, heat-resistant ohmic metal (by using Le),
Compared to the embodiment shown in FIG. 1, the annealing step can be omitted.

The MFiS FET fabricated by the above procedure has a high degree of 71
(Although there is no protruding portion below the active layer α2 of 1G, the high concentration layer tte has a structure that is continuous with the active layer a2 in the lateral direction.

Next, a case where the structure of the present invention is applied to g/D Mg3 PET will be explained based on FIG. 3.

E/D MFiS FBT is enhancement type FgT
It is generally assumed that the enhancement type FIT functions as a switching element and the depletion type FF1T functions as a load.

Therefore, the enhancement type FETK of the present invention, which is a switching element, was therefore applied here.

In the figure, C11 is a semi-insulating GaAs substrate, C is an active layer of an enhancement type FFmT, and ■ is an active layer of a depletion type FET (which is formed deeper than the active layer to realize a depletion type). ), l,
! 4 is a gate electrode, ■ is a side wall, (to) is a high concentration layer, and the surface is an ohmic electrode.The manufacturing method and materials are the same as those in the embodiment shown in FIG.

Incidentally, the high-temperature layer may be realized using a heat-resistant ohmic metal as shown in FIG.

The enhancement type FET in this B/D MBS FET has no protruding portion of the high concentration layer 4 below the active layer 32, and moreover, the high concentration layer has a structure that is continuous with the active layer in the lateral direction. .

(G) Effects of the Invention As is clear from the above description, the present invention can eliminate the short channel effect without increasing the series resistance.
The performance of the Schottky barrier field effect transistor can be improved.

[Brief explanation of the drawing]

FIGS. 1(a) to (7) are process explanatory diagrams of one embodiment of the present invention, FIGS. 2(a) to (e) are process explanatory diagrams of another embodiment of the present invention, and FIG. /D Cross-sectional view of MES FET,
FIG. 4 is a cross-sectional view of a conventional MES FET. 111 (111 (211-... semi-insulating substrate, 121
G2) eJ...active layer, (31[13C1!4...
Gate electrode, (4a) (14a)...side wall,
(6) αe4...high concentration layer.

Claims (1)

[Claims] 1. Consisting of an active layer formed on a semi-insulating substrate, a gate electrode provided on this active layer, and an insulating film formed on both sides of the gate electrode and on the active layer. comprising a sidewall, a high concentration layer formed adjacent to the active layer and the sidewall and at approximately the same depth as the active layer, and an ohmic electrode provided on the high concentration layer. A short-barrier field effect transistor characterized by: 2. An active layer formed on a semi-insulating substrate, a gate electrode provided on this active layer, and a heat-resistant ohmic layer formed adjacent to the active layer and at approximately the same depth as the active layer. 1. A Schottky barrier field effect transistor comprising: a highly doped layer consisting of a metal and an ohmic region.