JPH0245387B2 - - Google Patents

Info

Publication number
JPH0245387B2
JPH0245387B2 JP54151447A JP15144779A JPH0245387B2 JP H0245387 B2 JPH0245387 B2 JP H0245387B2 JP 54151447 A JP54151447 A JP 54151447A JP 15144779 A JP15144779 A JP 15144779A JP H0245387 B2 JPH0245387 B2 JP H0245387B2
Authority
JP
Japan
Prior art keywords
phase
clock
circuit
output
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP54151447A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5675744A (en
Inventor
Tetsumasa Ooyama
Akihiko Takada
Ikuo Washama
Katsumi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP15144779A priority Critical patent/JPS5675744A/ja
Publication of JPS5675744A publication Critical patent/JPS5675744A/ja
Publication of JPH0245387B2 publication Critical patent/JPH0245387B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP15144779A 1979-11-22 1979-11-22 Digital phase control circuit Granted JPS5675744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15144779A JPS5675744A (en) 1979-11-22 1979-11-22 Digital phase control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15144779A JPS5675744A (en) 1979-11-22 1979-11-22 Digital phase control circuit

Publications (2)

Publication Number Publication Date
JPS5675744A JPS5675744A (en) 1981-06-23
JPH0245387B2 true JPH0245387B2 (cs) 1990-10-09

Family

ID=15518790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15144779A Granted JPS5675744A (en) 1979-11-22 1979-11-22 Digital phase control circuit

Country Status (1)

Country Link
JP (1) JPS5675744A (cs)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2524983B2 (ja) * 1986-09-01 1996-08-14 古河電気工業株式会社 小径伝熱管

Also Published As

Publication number Publication date
JPS5675744A (en) 1981-06-23

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