JPH0245374B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to pulse circuits, and more particularly to complementary insulated gate field effect transistor circuits (hereinafter referred to as complementary insulated gate field effect transistor circuits).
Regarding pulse circuits including CMOSFET circuits.

CMOSFET circuits have characteristics such as low power consumption, high noise margin, and wide operating range, and are widely used.

By connecting a charging circuit or a discharging circuit consisting of a resistor R and a capacitor C to the input portion of the CMOSFET circuit, a pulse circuit that performs a predetermined time axis operation on the input signal of a one-shot circuit, a delay circuit, etc. can be created. Conventionally, in such a circuit, the input waveform is rounded by the time constant, and the rounding is similar to that of CMOS
This causes an increase in power consumption in the circuit. Now, the power consumption of the CMOS inverter circuit will be described using FIGS. 1 and 2. Input IN
When is at V _DD level, P channel MOSFET1
is non-conducting (hereinafter referred to as OFF), N channel
MOSFET2 conducts (hereinafter referred to as ON), but
Unless the output is loaded, the current will be less than V _DD .
Does not flow to V _SS . Also, when the input is at V _SS level,
P-channel MOSFET1 turns on, and N-channel MOSFET1 turns on.
MOSFET2 is turned off and current will not flow from V _DD to V _SS unless a load is applied to the output. When the input is stable in this way, there is only a slight leakage current from the reverse-biased PN junction and gate leakage current due to dirt on the gate surface, and only a current on the order of nanoamperes flows. Considering the case where the input level changes, the current that charges and discharges the load capacitance connected as a load, and the P channel current that changes during switching.
There is a current (through current) that flows from V _DD to V _SS when the MOSFET and N-channel MOSFET are turned on at the same time.

The power consumption Pdyn during charging and discharging is, if the input is a square wave with a duty of 50%, C _L · V _DD ² · f ₀ , and if the load capacitance C _L and the power supply voltage V _DD are constant, the frequency is f ₀ . becomes proportionally larger.

Also, P channel MOSFET and N channel
The current flowing from V _DD to V _SS when the MOSFETs become conductive at the same time differs depending on the impedance of each transistor when it is ON.

Therefore, the total power consumption is P _D = P _dyo + P _Q + P _S. However, P _dyo is power consumption during operation, P _Q is static power consumption, and P _S is power consumption during switching.
However, the power consumption P _S during switching varies depending on the ON resistance of each transistor. When the actual input level V _IN is V _DD - | V _TP | < V _IN (however, V _TP is P
channel MOSFET threshold voltage), P channel
When the MOSFET is in the OFF state, almost no current flows from V _DD to V _SS , and even when V _IN < V _TN (where V _TN is the threshold voltage of the N-channel MOSFET), N
The channel MOSFET is in the OFF state, and almost no current flows from V _DD to V _SS . However, when the input level V _TN < V _IN < V _DD − | V _TP |, that is, the input voltage V _IN is equal to the threshold voltage of the N-channel MOSFET.
When V _TN is exceeded, the current gradually begins to flow, and the input voltage further increases until around V _DD /2 (logical threshold voltage), where both transistors are turned on and the through current reaches its maximum, and the input voltage further increases. When the current rises, the P-channel MOSFET begins to turn off and the current decreases. This situation is shown in FIGS. 2 and 3. If the input waveform is sluggish like this, both the P-channel MOSFET and N-channel MOSFET
The drawback is that it stays on for a long time and consumes a lot of power.

For this reason, waveforms with short rise and fall times are desirable for input in MOSFET circuits, but due to the circuit configuration, power consumption during switching increases in circuits that connect an RC circuit to the input.
The low power consumption characteristic of CMOSFET circuits is lost.

The present invention is a CMOS device with an RC circuit connected to the input side.
The purpose is to reduce power consumption during switching of a pulse circuit that includes an inverter and performs a predetermined time base operation on an input signal.

According to the present invention, the output of a logic circuit has an inverter made of complementary insulated gate field effect transistors connected to the input side of a charging circuit or a discharging circuit having a time constant means, and whose input terminal is not in a floating state. In a pulse circuit that is connected to the terminal and generates a pulse signal of a predetermined width determined by the time constant means in response to an input signal, the pulse output of the output stage inverter is received at the gate, and the pulse output of the output stage inverter is connected to the gate. There is obtained a pulse circuit characterized in that a field effect transistor that turns on after the pulse width is determined is connected between the input terminal of the output stage inverter and the power supply.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 4 is a circuit connection diagram showing a typical example of a conventional one-shot circuit, and FIG. 5 shows operating waveforms at each point. In FIG. 5, paying attention to the input waveform 6 of the CMOS inverter 4, when the voltage waveform exceeds the logical threshold voltage of the inverter 4, the output of the inverter 4 becomes "L" level. However, capacitor C is still being charged, and while both FETs that make up inverter 4 are in the ON state, the through current continues to flow, and when input voltage 6 reaches the V _DD level, it is completely turned OFF.
becomes. After the logic threshold voltage is exceeded, there is no need to continue charging with the RC time constant as shown in the figure, and if the voltage level can be suddenly raised to the V _DD level, the through current of the CMOS inverter can be reduced.

FIG. 6 is a circuit connection diagram showing one embodiment of the present invention, in which a P-channel MOSFET 7 is connected as a pull-up resistor between the RC time constant circuit and the input side of the inverter 4. and the gate are connected to the input of the inverter, the power supply voltage V _DD and the output of the inverter 4, respectively. The other features are the same as the conventional one-shot circuit shown in FIG. Now input IN
changes from “L” to “H”, the output of the NOR circuit (NOR circuit) 3 changes from “H” to “L”, and the input side potential of the inverter 4 changes from “H” to “L”. After that, it starts to rise due to charging with a time constant determined by RC. The output OUT changes from "L" to "H", but it becomes "L" when the input side potential of the inverter 4 reaches the logic threshold of the inverter 4.
become the level. Then, the P-channel MOSFET 7 begins to conduct, and as a result, the input side potential of the inverter ₄ is quickly pulled up to _VDD , and the through current of the inverter 4 also rapidly decreases. FIG. 7 shows the operating waveforms at each point. In Figure 7, the dotted line is P
This is a waveform when channel MOSFET 7 is not connected. If the rise time of input IN is short, the through current I _DD will flow for only a short time when IN rises, and after all, the power consumption due to through current in a one-shot circuit can be reduced by approximately half by applying the present invention. .

FIG. 8 is a circuit connection diagram of a monostable multivibrator which is another embodiment of the present invention, in which the input 9 of the CMOS inverter 8 also falls and becomes "L" as the input signal falls. Output 10 of inverter 8 is “H”
As a result, the P channel MOSFET 11 is turned off. In this state, _C1 is charged, and when it is charged until it exceeds the logic threshold of inverter 8, inverter 8
Output 10 changes to “L” and becomes P channel.
MOSFET11 turns on. As a result, the input potential of inverter 8 is quickly pulled up to _VDD .
While the output 10 of the inverter 8 is "H", the charge charged in the capacitor _C2 via the reverse current prevention diode 12 is discharged via the resistor _R2 when the output 10 of the inverter 8 becomes "L", and is transferred to the CMOS inverter. When the input potential 14 of 13 becomes below the logic threshold, OUT changes from "L" to "H", and the N-channel MOSFET 15 begins to conduct and the input potential 14
Pull down to V _SS . In this way, the power consumption due to the through current of the CMOS inverters 8 and 13 is reduced to approximately half of the conventional power consumption due to the pull-up action of the P-channel MOSFET 11 and the pull-down action of the N-channel MOSFET 15, respectively. FIG. 9 is a diagram showing operating waveforms at each point, and the dotted line is the waveform when there is no pull-up or pull-down. Furthermore, _IDD
is the current flowing between the power supplies.

As explained above, according to the present invention, an RC time constant circuit is connected to the input side of a MOS inverter,
A CMOS inverter is configured in a pulse circuit that performs a specified time axis operation on an input signal.
The time during which both FETs are conductive can be kept to the necessary minimum, which has a significant effect on reducing the power consumption of pulse circuits.

[Brief explanation of the drawing]

Figure 1 is a circuit connection diagram of a CMOS inverter, Figure 2 is a diagram showing the input/output characteristic curve (solid line) of a CMOS inverter, and the relationship between through current I _DD and input voltage V _IN , and Figures 3 a and b are CMOS A diagram showing an example of the temporal change in the input voltage V _IN of the inverter and a temporal change in the through current I _DD . Figure 4 is a circuit connection diagram showing a conventional one-shot circuit. Figure 5 shows each of the circuits in Figure 4. Figures 6 and 7 are circuit connection diagrams showing an embodiment of the present invention and diagrams showing operation waveforms at each point, and Figures 8 and 9 are diagrams showing operation waveforms at each point, respectively. FIG. 7 is a circuit connection diagram showing another embodiment and a diagram showing operation waveforms at each point. 1...P channel MOSFET, 2...N channel
MOSFET, 3...NOR circuit, 4, 8, 13
...CMOS inverter, 5...4 output, 6...4 input, 7, 11...P channel MOSFET, 9...8
input, 10...output of 8, 12...diode, 1
4...13 inputs, 15...N-channel MOSFET,
V _DD ...High potential power supply, V _SS ...Low potential power supply, IN...Input terminal, OUT...Output terminal.

Claims (1)

[Claims] 1. An inverter consisting of a complementary insulated gate field effect transistor whose input side is connected to a charging circuit or a discharging circuit having a time constant means, and whose input terminal is connected to the output terminal of a logic circuit such that it is not in a floating state, In a pulse circuit that generates a pulse signal with a predetermined width determined by the time constant means in response to an input signal, the pulse output of the inverter in the output stage is received at a gate, and the pulse width of the pulse output of the inverter in the output stage is determined. 1. A pulse circuit characterized in that a field effect transistor that is later turned on is connected between an input terminal of the output stage inverter and a power source.