JPH0243197B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a musical tone signal generating device, and more particularly to a musical tone signal generating device that performs interpolation between musical waveform sample point amplitudes in accordance with the range of a musical tone to be generated. [Prior Art] A typical method for generating a musical sound waveform sample point amplitude signal based on phase information that changes in accordance with the pitch of a musical sound to be generated is to generate a musical sound waveform that is divided into a specific number of sample points. is stored in a memory and read out according to the phase information. Looking at the reading of musical sound waveforms with the same note name in different octaves, the amount of phase change in phase information per sampling time increases as the octave goes up, and decreases as the octave goes down. For this reason, when reading out a musical sound waveform in the bass range, the same sample point amplitude value may be read out repeatedly over multiple sampling times. This means that the effective sampling frequency is reduced by the amount that the same sample point amplitude value is read out repeatedly. for example,
If a different sampling point amplitude value is read each time according to the sampling clock pulse of frequency _fs , the effective sampling frequency of the read musical waveform signal is _fs , but the sampling clock pulse Therefore, if the same sample point amplitude value is read out twice, the effective sampling frequency of the read out musical waveform signal will drop to f _s /2. Note that the effective sampling frequency here refers to the frequency at which the sample point amplitude value actually changes in the obtained musical waveform signal. As mentioned above, when the effective sampling frequency decreases, no matter how high the nominal sampling frequency (that is, the frequency of the sampling clock pulse), the effective sampling frequency decreases and the band where aliasing noise occurs becomes lower. There was a problem that aliasing noise was likely to occur. Such a problem may occur not only in the waveform memory reading method as described above, but also in any other musical waveform sample point amplitude signal generation method. On the other hand, it has been known in the past to perform sampling densely by interpolating between each sample point of a once generated musical waveform sample point amplitude signal. For example, in Japanese Patent Publication No. 53-30015,
It is disclosed that the higher the range of the musical sound to be generated, the more densely the interpolation between sample points is performed.As a result, the musical sound waveform in the high range becomes a smooth waveform with few high frequency components, and the high range We are trying to solve the problem of aliasing noise. However, in such conventional technology, the above-mentioned reduction in the effective sample point frequency in the low frequency range and the accompanying problem of aliasing noise in the low frequency range are not addressed at all, and it is difficult to solve this problem. Can not. [Problems to be Solved by the Invention] This invention has been made to solve the above-mentioned problems. It is an object of the present invention to provide a musical tone signal generating device that has the following characteristics. [Means for Solving the Problems] The musical tone signal generating device according to the present invention generates interpolation information that performs interpolation more densely as the tone range becomes lower, depending on the tone range of the musical tone to be generated. The present invention is characterized by comprising a generating means and an interpolating means for interpolating the amplitude between at least two sample points of the generated musical waveform sample point amplitude signal based on the interpolation information. Preferably, the interpolation information generating means generates the interpolation information when the range of the musical tone to be generated is lower than a predetermined reference range. As an example, this interpolation information determines the number of interpolation steps depending on the musical range, and the number of steps increases as the musical range becomes lower. In this case, it is preferable to set the range in units of one octave as this simplifies various processing, but it is not necessarily necessary to set the range in units of one octave, and it may be set in units of two octaves or half octaves. You may also do so. According to another aspect of the invention, a musical tone signal generating device includes a note clock generating means for generating a note clock pulse corresponding to a relative note name within an octave range of a musical tone to be generated; numerical data generating means for generating numerical data corresponding to the octave range to which it belongs; address signal generating means for generating an address signal by adding or subtracting the numerical data at the generation timing of the note clock pulse; a waveform generating means for generating a musical tone waveform sample point amplitude signal in accordance with an integer part of an address signal; and a waveform generating means for generating a musical tone waveform sample point amplitude signal corresponding to an adjacent integer part address generated by the waveform generating means to generate two musical tone waveform sample point amplitude signals corresponding to the address signal. It is characterized by comprising an interpolation means for interpolating according to the decimal part of. [Operation] Interpolation information corresponding to the range of musical tones to be generated is generated by the interpolation information generating means, and the amplitude between sample points of the musical sound waveform is interpolated in the interpolation means based on this interpolation information. When interpolation is performed, the actual number of sample points increases by a number corresponding to the number of interpolation steps. Therefore, if such interpolation is performed in a predetermined bass range depending on the sound range, the effective sampling frequency can be increased, thereby solving the problem of aliasing noise. To explain this point with reference to FIG. 10, a indicates an example of a portion of the amplitude of a musical waveform sample point in a predetermined reference octave, and its effective sampling frequency is assumed to be _fs . b shows an example of the amplitude of a musical waveform sample point one octave below the reference octave, and this is before interpolation.
If the sampling time of a is one sampling time, the same sample point amplitude value continues over two sampling times. Therefore, its effective sampling frequency is f _s /2. c shows an example of the musical waveform sample point amplitude when the sample points of b are interpolated in two steps, and the amplitude value changes at each sampling time. Therefore, its effective sampling frequency is _fs . d
Similarly, e shows an example of the amplitude of a musical sound waveform sample point two octaves below the reference octave before interpolation, and e shows an example of the amplitude of a musical sound waveform sample point two octaves below the reference octave after interpolation. The effective sampling frequency of d is f _s /4, and since e interpolates between the sample points of d in four steps, its effective sampling frequency is f _s . As is clear, c and e show an example of interpolation according to the present invention, which increases the effective sampling frequency in the bass range, for example, by making the effective sampling frequency common in all ranges. I can understand that it can be done. According to another aspect of the invention, the fractional part of the address signal generated by the address signal generating means is used as an interpolation parameter. This address signal is an addition/subtraction value of numerical data corresponding to an octave range, and if this numerical data includes a decimal part, the address signal also includes a decimal part. Therefore, if this numerical data includes a decimal part according to the octave range, interpolation can be performed according to the range of the musical tone to be generated, as described above. Note that the octave range in this case is not limited to one octave unit, but may be two octave units, etc., as described above. [Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. [Description of overall configuration of one embodiment] In FIG. 1, a keyboard 10 is equipped with a plurality of keys for specifying the pitch of a musical tone to be generated.
The key press detection circuit 11 detects key presses and key releases on the keyboard 10, and provides a signal corresponding to the detected key presses and key releases to the sound generation assignment circuit 12. The sound generation assignment circuit 12 is for allocating the sound of a musical sound corresponding to a pressed key to one of a plurality of musical sound generation channels, and generates a key code indicating the key assigned to that channel at the time division timing corresponding to each channel. It outputs a key-on signal KON indicating whether or not the KC and the key are being pressed continuously. The key code KC is given to a P number generation circuit 13 and an octave data generation circuit 14.
The P number generation circuit 13 receives the input key code.
A P number having a value corresponding to the KC pitch name (that is, the pitch name of the musical tone to be generated) is generated. The P number will be described later. The octave rate data generation circuit 14 generates numerical data, ie, octave data RATE, corresponding to the octave of the musical tone to be generated based on the input key code KC. Here, the range of one octave is not necessarily limited to the range of one octave from the pitch name C, but may be the range of one octave from any pitch name. As will be clear from the description below, this octave data generation circuit 14 functions as interpolation information generation means for octaves lower than a predetermined reference octave. That is, numerical data corresponding to an octave lower than the reference octave, that is, rate data RATE, functions as interpolation information corresponding to that octave. The note clock generating circuit 15 generates a note clock pulse having a frequency corresponding to the note name of the musical tone to be generated in accordance with the P number given from the P number generating circuit 13. This note clock pulse is generated by the address signal generation circuit 16.
Since it functions as a signal requesting to change the address signal by adding (or subtracting) the rate data RATE described above, it will also be referred to as an address change request signal CRQ. The address signal generation circuit 16 generates rate data when the address change request signal CRQ is applied.
An address signal is generated by adding (or subtracting) RATE. Therefore, the address signal increases (or increases) by the value of the rate data RATE (by the value corresponding to the octave) every time the address change request signal CRQ is applied (that is, every time the note clock pulse is generated). Decrease. As is commonly known, the address signal repeatedly increases (or decreases) by a predetermined modulo number. The address signal generated from the address signal generation circuit 16 can be divided into an integer part and a decimal part, and the integer part specifies the sample point order, that is, the phase of the musical waveform sample point amplitude signal to be generated from the tone generator 17. phase address signal
It is supplied to the tone generator 17 as PHA, and its fractional part is supplied to pitch synchronization/interpolation circuit 18 as interpolation address data INT indicating an interpolation address. Note that in the case of linear interpolation, the interpolation address data INT can be used as is as an interpolation coefficient. The pitch synchronization/interpolation circuit 18 resamples the musical waveform sample point amplitude signal generated from the tone generator 17 in synchronization with its pitch, that is, the pitch (this is referred to as pitch synchronization operation), and Interpolate the state musical waveform sample point amplitude signal between adjacent sample points (between adjacent integer part addresses) with the interpolated address data.
Performs interpolation according to INT. The above-mentioned octave rate data RATE consists of an integer part and a decimal part, and it is the decimal part data that functions as the above-mentioned interpolation information. The decimal part of the address signal, that is, the interpolated address data INT, is
It is obtained by calculating the decimal part of this rate data RATE. As will become clear from the description below, the octave rate data RATE has a fractional value when the octave of the musical tone to be generated is lower than a predetermined reference octave.
If it is larger than that, it does not have a decimal value. Therefore, when the octave is lower than the reference octave, interpolation address data INT is generated and interpolation is performed by the interpolation circuit 18, but when it is lower than the reference octave, interpolation address data INT is not generated and no interpolation is performed. The musical tone signal output from the pitch synchronization/interpolation circuit 18 is converted into an analog signal by a digital/analog converter 19 and then sent to a sound system 20. The timbre selection circuit 21 is for selecting the pitch of the musical tone to be generated, and timbre information TC indicating the selected timbre is provided to the tone generator 17 and other circuits. The operation of each circuit from the sound generation allocation circuit 12 to the pitch synchronization/interpolation circuit 18 is performed on a time-division basis for each channel. The timing signal generating circuit 22 generates various timing signals, master clock pulse φ _M , and other clock pulses for controlling the time division operations of each circuit. Furthermore, in the embodiment shown in FIG. 1, special measures have been taken regarding the pitch synchronization operation and time division operation speed described above. A note clock generating circuit 15 is provided for pitch synchronization, and generates a note clock pulse, ie, an address change request signal CRQ, having a frequency corresponding to the note name of the musical tone to be generated.
If the address signal is changed in accordance with the generation timing of this address change request signal CRQ, the effective sample frequency of the musical waveform signal generated based on this address signal and its pitch will be harmonized, and pitch synchronization will be achieved. . However, as will be clear from the description below, in this embodiment, pitch synchronization is not achieved at the stage of the address signal generation circuit 16 and tone generator 17, and the pitch synchronization/interpolation circuit 18
Pitch synchronization is now achieved. By the way, the note clock generation circuit 15 has to generate note clock pulses corresponding to various note names for each channel in a time-division manner based on a common master clock pulse φ _M , and also requires precision of pitch synchronization. In order to increase the frequency, it is desirable that the frequency of the note clock pulse is also relatively high. Therefore, the note clock generating circuit 15 is required to operate at relatively high-speed time division timing.
Further, the pitch synchronization/interpolation circuit 18 for realizing pitch synchronization is also required to operate at high speed time division timing similar to the note clock pulse. On the other hand, the sound generation allocation circuit 12 and the tone generator 17 are not required to operate at such high-speed time-sharing timing, and rather, it is preferable for the time-sharing timing to be relatively slow in terms of circuit configuration or musical tone generation calculation processing. Therefore, in this embodiment, the necessary circuits are operated at two time-division operation speeds: high speed and low speed. In other words, the sound generation allocation circuit 12 and the tone generator 17 perform time-division processing for each channel at low-speed time-division timing, and the note clock generation circuit 15 and pitch synchronization/interpolation circuit 18 perform time-division processing for each channel at high-speed time-division timing. I am trying to process it. The output of the sound generation allocation circuit 12 is output at slow time division timing. However, since the note clock generating circuit 15 operates at a high speed time division timing, in order to match this, the P number generation circuit 13 is provided with means for converting the time division speed of the signal from low speed to high speed. In addition, the output of the note clock generation circuit 15
CRQ is also a high-speed time division timing signal, so
In order to match the rate data RATE with high-speed time-division timing, the octave rate data generation circuit 14 is also provided with means for converting the time-division speed of the signal from low to high speed. Inside the address signal generation circuit 16, an address change request signal, which is a high-speed time division timing signal, is used.
An address signal must be generated based on CRQ and rate data RATE, but since the tone generator 17 that uses this address signal (especially its integer part) operates at low-speed time division timing, the time division speed of the signal is Means for converting from high speed to low speed is provided inside the circuit 16, and outputs at least the integer part of the address signal, that is, the phase address signal RHA, at low speed time division timing. The pitch synchronization operation in the pitch synchronization/interpolation circuit 18 must be performed at high-speed time division timing similar to the note clock pulse, that is, the address change request signal CRQ, and in order to perform interpolation without damaging the pitch synchronization state. It is also necessary to perform interpolation operations at high-speed time division timing. Therefore, inside the circuit 18, there is provided means for converting the tone waveform sample point amplitude signal of low speed time division timing sent from the tone generator 17 into high speed time division timing. Note that since the interpolation operation is performed at high-speed time division timing, the interpolated address data INT generated from the address signal generation circuit 16 may remain at high-speed time division timing. Next, detailed examples of each circuit in FIG. 1 will be explained. (Explanation of time division timing) First, an example of low speed and high speed time division timing will be described with reference to FIG. 2. The high-speed time division timing is formed by using one period of the master clock pulse φ _M as one time slot. As an example, assuming that the number of sound generation channels is four, the time clocks of the first to fourth channels in the high speed time division timing, that is, the high speed channel timings are as shown in FIG. 2b. Therefore, the sampling period of one note at high speed time division timing is four times the master clock pulse _φM . Figure 2 d shows the master clock pulse φ _M at 16
Indicates a slow clock pulse φ ₁ with twice the period,
Low-speed time division timing is set with one period of this low-speed clock pulse _φ1 as one time slot. FIG. 2e shows the channel name of the key code KC output from the sound generation assignment circuit 12 of FIG. 1 according to this low-speed time division timing.
FIG. 2c shows a channel synchronization pulse CH, which is used when converting the time division speed of a signal from slow to fast or vice versa. This pulse CH is applied to each channel 1 to 64 during one round of low _{-speed channel timing (64 cycles of master clock pulse φ M )} .
It consists of a total of four pulses that are generated only once corresponding to the four high-speed time division timings. For example, one pulse is generated at the high-speed time division timing of channel 1, and its 17φ _M (master clock pulse φ _M
One pulse is generated at the high-speed time division timing of channel 2 after 17 cycles), and one pulse is generated at the high-speed time division timing of channel 3 after 17φ _M , and then one pulse is generated at the high-speed time division timing of channel 4 after 17φ _M. One pulse is generated at the timing, and the 13φ _M
Returning to the high-speed time division timing of channel 1 (13 cycles of master clock pulse φ _M ) later, one pulse is generated. FIG. 2f shows the timing at which the inverted key-on pulse is generated from the sound generation assignment circuit 12. This pulse is normally "1", but when a new press key is assigned to a certain channel, it becomes "0" only once in accordance with the generation timing of the channel synchronization pulse CH corresponding to that channel. (Explanation of P number) P number is one of musical sound waveforms having frequencies corresponding to each note name C to B in a certain standard octave.
This is a number indicating the number of sample points in a cycle. Since it is possible to time-divisionally generate multiple tones with arbitrary note names, the basic sampling frequency is the same for all note names, and as mentioned above, this is a period four times the master clock pulse φ _M. It is something that has. On the other hand,
Since the basic sampling frequency is common,
The P number of each pitch name indicates a different value depending on the frequency of the pitch name. Let fn be the frequency of a certain note name in the standard octave, and let fc be the common sampling frequency mentioned above, then P corresponding to that note name is
The number is determined as follows. P number = fc÷fn...(1) Here, the common sampling frequency fc is fc=
Assuming that the frequency fn of pitch name A is 785.54kHz and fn = 440Hz (that is, A4 note), the P number of pitch name A is
From the above formula, P number of pitch name A=785540÷440=1785. On the other hand, assuming that the number of sample points of different sample point amplitude values per period of musical sound waveform that can be generated within the tone generator 17 is 64, the effective sampling frequency fe of the frequency fn is fe=fn×64...(2) So, when fn=440Hz, fe=440×64=28160Hz. Similarly, the P number and effective sampling frequency fe of each pitch name in a certain reference octave can be determined as shown in the table below. In this example, the standard octave is one octave from note G4 to note F#5.

[Table] (Description of Note Clock Pulse) In the note clock generation circuit 15 (FIG. 1), the note clock pulse, that is, the address change request signal CRQ, uses the common sampling frequency fc established based on the master clock pulse _φM . It is obtained by dividing the frequency according to the P number. As is clear from the above, the P number is the number of cycles of the common sampling frequency fc in one cycle waveform, that is, the number of sample points.On the other hand, the effective number of sample points per cycle of the musical sound waveform that can be generated by the tone generator 17 is As mentioned above, it is 64. Therefore, if the frequency division number for dividing the common sampling frequency fc is frequency division number = P number ÷ 64...(3), then the frequency division output is 64 per period of musical tone.
pulses can be obtained, thereby establishing all 64 effective sample points. When the common sampling frequency fc is divided by the frequency division number determined in this way, the above (1), (2),
From formula (3), fc ÷ frequency division number = (fn x P number) ÷ (P number ÷ 64) = fn - 64 = fe...(4) The sample point address is changed by this frequency division output. By this, the effective sampling frequency fe can be established. The effective sampling frequency fe established in this way is in harmony with the pitch name frequency fn, and pitch synchronization is achieved.
A note clock pulse generated from the note clock generation circuit 15, that is, an address change request signal.
CRQ is a frequency-divided output signal as shown in equation (4) above, that is, a signal having an effective sampling frequency fe. By the way, the frequency determined by the above equation (3) is not necessarily an integer and often includes a decimal number. for example,
In the case of pitch name A, the frequency division number = 1785÷64≒27.89. Therefore, the frequency dividing operation in the note clock generation circuit 15 is to appropriately divide the frequency by two integers close to the frequency division number determined by equation (3), and the average result is the frequency division number determined by equation (3). The same result as dividing by the number of cycles is obtained. (Detailed Example Description of P Number Generation Circuit 13 and Note Clock Generation Circuit 15) In FIG. Number memory 2
3 and a low/high speed conversion section 24. Low/
The high-speed conversion unit 24 includes a selector 25 into which the output of the P number memory 23 is input to the "1" input, and a 4-stage shift register 2 corresponding to the number of channels 4.
6, and the output of the shift register 26 is circulated through the "0" input of the selector 25. A channel synchronization pulse CH (see Figure 2 c) is input as a selection control signal to the selector 25, and when it is "1", the "1" input is selected, and when it is "0", the "0" input is selected. .
The shift register 26 receives the master clock pulse φ _M
The shift is controlled by The P number memory 23 is connected to the sound generation assignment circuit 12.
The key code KC of each channel, which is output at low-speed time division timing as shown in FIG. 1 to e in FIG. The read P number is a signal with low-speed time division timing similar to that shown in FIG. 2e. The low/high speed converter 24 converts the read P
This converts the time division timing of numbers at high speed. That is, the P number read out from the memory 23 for channel 1 with low-speed timing is selected by the selector 25 when the channel synchronization pulse CH becomes "1" at the timing of high-speed channel 1, and is stored in the shift register 26. be included. Similarly, when the P number read at the timing of other low-speed channels 2, 3, and 4 becomes "1" at the timing of the corresponding high-speed channels 2, 3, and 4, the selector 25
is selected and taken into the shift register 26.
The P number taken into the shift register 26 is then sent to the pulse CH at high-speed timing of that channel.
The signal is cyclically held in the shift register 26 via the "0" input of the selector 25 until the time when the signal becomes "1". In this way, 4 of the shift registers 26
The two stages contain P numbers corresponding to the note names of keys assigned to channels 1 to 4, and are shifted according to the master clock pulse φ _M at a period four times that of the master clock pulse φ M (that is, the common sampling frequency fc (with a period of ) is repeatedly output. Therefore, the timing of the P number of each channel output from the shift register 26 is as shown in FIG. 2b.
This P number consists of, for example, a 12-bit binary coded signal. In FIG. 3, the note clock generating circuit 15
is an adder 27 that inputs the P number output from the shift register 26, a selector 28 that inputs the output of this adder 27 to the "0" input, and a 4-stage shift register that inputs the output of this selector 28. 29, a gate 30 which gates the lower 6 bits (decimal part) of the output of the shift register 29 and supplies it to the other input of the adder 27, and inputs the upper 7 bits (integer part) of the output of the shift register 29. It includes an adder 31 that adds an all "1" signal consisting of 7 bits, all of which are "1".
Although the P number itself is a 12-bit binary coded signal, the output of adder 27 consists of a 13-bit signal including one extra bit as a carry signal bit. The inverted key-on pulse (its timing relationship is shown in FIG. 2f) and the signal output from the carry-out output CO of the adder 31 are input to an AND circuit 32.
The output of 2 is applied to the selection control input of the selector 28. When the output signal of the AND circuit 32 is "0", the signal given from the adder 27 to the "0" input of the selector 28 is selected, and when it is "1", the signal given to the "1" input is selected. be done. selector 28
A 13-bit signal consisting of the lower 6 bits (decimal part) of the output of shift register 29 and 7 bits (integer part) of adder 31 is applied to the "1" input of . Selector 28, shift register 29, adder 3
Part 1 is a circuit for establishing a frequency division number as shown in equation (3) above according to the P number, and dividing the common sampling frequency fc according to the integer part of this frequency division number. . The adder 27 is for adjusting the value of the integer part according to the decimal part of the frequency division number. In equation (3) above, the divisor 64 is ²⁶ , so there is no need to perform any special division to find the division number, and the P number can be handled simply by treating the lower 6 bits of the P number as the decimal part. It is possible to establish a frequency division number. Therefore, adder 27, selector 28
Of the 13 bits of the output signal from the shift register 29, the lower 6 bits are the weight of the decimal part, and the upper 7 bits are the weight of the integer part. Adding all "1" signals in the adder 31 is equivalent to subtracting 1. Therefore, the adder 31 effectively subtracts 1 from the integer value output from the shift register 29. The subtraction result of the adder 31 is returned to the "1" input of the selector 28 together with the 6-bit data of the decimal part that was not operated, and is inputted to the adder 31 again via the shift register 29. Since the shift register 29 is shift-controlled by the master clock pulse φ _M , the signals of the same channel are transferred to the shift register 29.
The period output from is the master clock pulse φ _M
, that is, the period of the common sampling frequency fc. At the beginning of a key press, an inverted key-on pulse is generated at the channel timing assigned to that key.
KONP becomes "0" only once, and at this time, the P number of the key is selected via the "0" input of the selector 28. The integer part of this P number is provided from the shift register 29 to the adder 31, and 1 is repeatedly subtracted from the integer part at a cycle of the common sampling frequency fc. When the subtraction result of the integer part is a value of 1 or more, the carry-out signal "1" is constantly output from the carry-out output CO of the adder 31,
Since the condition of the AND circuit 32 is satisfied, the selector 28 continues to select the "1" input. When the output of the adder 31 eventually becomes "0" by repeating the subtraction, that is, the number of fc equal to the number of integer parts of the P number
When the frequency has elapsed, the carry-out signal of the adder 31 is not output, and the condition of the AND circuit 32 is not satisfied. At that time, the selector 28 is "0"
The input is selected, and the output of the adder 27, which is the sum of the P number and the lower 6 bits (decimal part data) of the output of the shift register 29, is selected. In this way, the P number whose value has been changed somewhat by the addition of the decimal part is given to the shift register 29, and the process of subtracting 1 from the changed integer value of the P number is repeated. In addition, gate 30 is an inverted key-on pulse.
KONP disables it only at the beginning of pressing the key,
At other times, the decimal part data is always sent to the adder 27.
give to Due to the addition of decimal part data to the P number in the adder 27, the integer value of the frequency division number actually used for frequency division may become one larger than the integer value of the frequency division number determined from the P number. For example, the P number of pitch name A is 1785, and its frequency division number is 27.89. Initially, the frequency is divided according to the integer value 27, but then it becomes 27.89 + 0.89 = 28.78,
The frequency will be divided according to the integer value 28. In this way, the common sampling frequency fc is divided according to a number that is equal to or 1 greater than the integer value of the frequency division number determined by the P number, and the average result is determined by the P number. A frequency division operation according to the frequency division number is achieved. The signal of the carry-out output CO of the adder 31 corresponds to the frequency-divided output, and the signal inverted by the inverter 33 is output as the note clock pulse, that is, the address change request signal CRQ. For better understanding, an example of changes in the output of the selector 28 will be shown using pitch name A as an example. The change timing is the cycle of the common sampling frequency fc.
The first is the frequency division number 27.89 corresponding to the P number 1785, then the integer value is decreased by 1 to 26.89, and then the integer values are decreased by 1 in sequence to 25.89, 24.89, 23.89, ...2.89, 1.89. . At the 27th cycle of fc, the value added to the "1" input of the selector 28 becomes 0.89, at this time the carry out signal becomes "0", the note clock pulse, that is, the address change request signal CRQ becomes "1", and the selector 28 outputs "1". 0” input. The “0” input of the selector 28 is given the value 28.78, which is the sum of the frequency division number 27.89 corresponding to the P number 1785 and the decimal value 0.89 given from the shift register 29. Therefore, 28.78
is output from the selector 28. After that, the output of the selector 28 is 27.78, 26.78, 25.78, 24.78,...
The number decreases by 1 sequentially to 2.78, 1.78, and the value added to the "1" input of the selector 28 at the 28th cycle of fc is
0.78, the carryout signal of the adder 31 becomes "0", and the note clock pulse, that is, the address change request signal CRQ is generated. At this time, the output of the adder 27 is 27.89+0.78=28.67, which is applied to the shift register 29 via the "0" input of the selector 28. After that, the output of the selector 28 is 27.67, 26.67, 25.67, 24.67,
...2.67, then 1.67, decreasing by 1 one by one. In this way, frequency division is performed using 27 or 28 as the frequency division number. (Detailed Example Description of Octave Rate Data Generating Circuit 14) In FIG. 4, the reference octave code generating circuit 34 generates a 3-bit octave code indicating a predetermined reference octave in accordance with the timbre selection information TC. This octave code and an F# note code consisting of 4 bits indicating the boundary between octaves are applied to the A input of the subtracter 35. Subtractor 35
The key code KC given from the pronunciation assignment circuit 12 (FIG. 1) is input to the B input of. The subtracter 35 performs subtraction AB to find the difference in octave of the musical tone to be generated from the reference octave. This octave difference can be distinguished by the upper 4 bits of the 7-bit output, which is the difference between 7-bit key codes consisting of a 3-bit octave code and a 4-bit note code. The subtraction result of the upper 4 bits is output. In addition, in this example, the octave boundary in the octave chord coding is between the B note and the C note, as is generally known, whereas in setting the standard octave, the octave boundary is shown in Table 1. As shown in , it is between the F note and the G note. Therefore, the subtracter 35 performs subtraction using all the bits of the key code. if,
When setting the reference octave, if the octave boundary is set between the B note and the C note as in the coding of octave codes, the subtracter 35 only needs to subtract between octave codes. In addition,
The reference octave code generation circuit 34 changes the reference octave according to the selected timbre, thereby realizing an octave shift of the key according to the timbre. As an example, a typical reference octave is the first
As shown in the table, it is in the range of G4 to F#5. The low/high speed converter 36 is the converter 2 shown in FIG.
It consists of a selector 37 and a shift register 38 configured similarly to 4. The octave shift data output from the subtracter 35 is converted into high-speed time division timing by this converter 36 and input to an octave rate conversion memory 39. The octave rate conversion memory 39 outputs octave rate data RATE as shown in the table below according to the input octave shift data.

〔Effect of the invention〕

As described above, according to the present invention, since interpolation is performed between musical waveform sample points according to the range of the musical sound to be generated, it is possible to prevent a drop in the effective sampling frequency in the bass range, thereby preventing the occurrence of aliasing noise. can be suppressed.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration block diagram showing one embodiment of an electronic musical instrument to which the present invention is applied, FIG. 2 is a timing chart of various timing signals to show an example of channel time division timing, and FIG.
FIG. 4 is a block diagram showing a detailed example of the P number generation circuit and note clock generation circuit in FIG. 1. FIG. 5 is a block diagram showing a detailed example of the octave data generation circuit in FIG. 6 is a block diagram showing a detailed example of the pitch synchronization/interpolation circuit shown in FIG. 1. FIG. 7 is a block diagram showing a detailed example of the interpolation circuit shown in FIG. 6. The figure is a block diagram showing an example of modification of the high/low speed converter in Fig. 5, and Fig.
10 is a block diagram showing another embodiment of the present invention, and FIG. 10 is a waveform diagram of a musical waveform sample point amplitude signal showing an example of interpolation between sample points according to an octave according to the present invention. 10... Keyboard, 11... Key press detection circuit, 12... Sound generation assignment circuit, 13... P number generation circuit, 14... Octave data generation circuit, 15, 86-1
~86-4...Note clock generation circuit, 16,9
0... Address signal generation circuit, 17, 92... Tone generator, 18, 94-1 to 94-4... Pitch synchronization/interpolation circuit.

Claims (1)

[Scope of Claims] 1. Phase information generating means that generates phase information that changes in accordance with the pitch of a musical tone to be generated; Waveform generating means that generates a musical waveform sample point amplitude signal in accordance with this phase information. , interpolation information generating means for generating interpolation information that performs interpolation more densely as the range becomes lower, according to the range of the musical sound to be generated; and a musical waveform sample point amplitude signal generated by the waveform generating means. interpolation means for interpolating the amplitude between at least two sample points of the tone signal based on the interpolation information. 2. The musical sound signal generating device according to claim 1, wherein the interpolation information generating means generates the interpolation information when the range of the musical sound to be generated is lower than a predetermined reference range. 3. The musical tone signal generating device according to claim 1 or 2, wherein the interpolation information determines the number of interpolation steps depending on the tone range when performing interpolation between the sample points. 4. The musical tone signal generating device according to claim 3, wherein the number of interpolation steps increases as the tone range becomes lower. 5. The phase information generating means causes the waveform generating means to generate the amplitude signal of all sample points when the range of the musical tone to be generated is below the reference range, but when it is higher than the reference range, the amplitude signal is generated in that range. 3. The musical tone signal generating apparatus according to claim 2, wherein said phase information is generated so as to generate said amplitude signal while skipping one or more sample points accordingly. 6. The musical tone signal generating device according to any one of claims 1 to 5, wherein the tone range is set in units of octaves. 7 Note clock generation means for generating a note clock pulse corresponding to a relative note name within the octave range of the musical tone to be generated, and numerical data generation means for generating numerical data corresponding to the octave range to which the musical tone to be generated belongs. means for generating an address signal by adding or subtracting the numerical data at the generation timing of the note clock pulse; and generating a musical waveform sample point amplitude signal according to the integer part of the address signal. A musical tone comprising a waveform generating means for generating a waveform, and an interpolating means for interpolating two musical waveform sample point amplitude signals corresponding to adjacent integer part addresses generated by the waveform generating means according to a decimal part of the address signal. Signal generator. 8. The musical tone signal generating device according to claim 7, wherein the numerical data corresponds to a shift in the octave range of the musical tone to be generated with respect to a predetermined reference octave range.