JPH0242769A - Manufacture of pin photodiode - Google Patents

Manufacture of pin photodiode

Info

Publication number
JPH0242769A
JPH0242769A JP63192854A JP19285488A JPH0242769A JP H0242769 A JPH0242769 A JP H0242769A JP 63192854 A JP63192854 A JP 63192854A JP 19285488 A JP19285488 A JP 19285488A JP H0242769 A JPH0242769 A JP H0242769A
Authority
JP
Japan
Prior art keywords
type
layer
light
pin photodiode
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63192854A
Other languages
Japanese (ja)
Inventor
Yuzaburo Ban
雄三郎 伴
Mototsugu Ogura
基次 小倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63192854A priority Critical patent/JPH0242769A/en
Publication of JPH0242769A publication Critical patent/JPH0242769A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To simplify a production process by a method wherein a semiconductor layer is grown epitaxially while an n-type impurity material and a P-type impurity material are being supplied simultaneously onto a photodetecting layer and a desired part is being irradiated with a beam. CONSTITUTION:When a part as a P-type impurity diffusion region 15 is grown epitaxially, a part other than the P-type impurity region 15 is irradiated with a beam 14; the part irradiated with the beam becomes an n-type and the non-irradiated part becomes the P-type 15; when an epitaxial growth operation has been finished, a P-type region is formed in a desired part. Accordingly, when a layer including the last P-type region 15 is grown, e.g., in the case of a pin photodiode, an n-type impurity material and a P-type impurity material are supplied simultaneously, and a part other than a part to be used as a photodetecting part is irradiated with a beam 14; a P-type region 15 is formed in the photodetecting part; as a result, a p-n junction is formed. In addition, when only the n-type impurity material whose optical resolving efficiency is large is supplied and the surface of a substrate 1 is irradiated with a beam, an n<+> type region 3 is formed in a desired part when an epitaxial growth operation has been finished. Thereby, the photodetector can be formed by only one epitaxial growth operation.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、光通信分野、光計測分野、光情報処理分野で
有用なpinフォトダイオードの製造方法に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a pin photodiode useful in the fields of optical communication, optical measurement, and optical information processing.

(従来の技術) 近年、様々な分野で半導体レーザと共に受光素子の需要
が高まり、各所で研究開発が活発に行われている。これ
まで、種々の受光素子の構造が提案され、そのなかのい
くつかは、製造プロセスのなかで、Znに代表されるp
型不純物の拡散工程、あるいはイオン注入工程がありそ
の良し悪しか受光素子特性を大きく左右している。例え
ば、通常のpinフォトダイオードのZn拡散によるp
n接合形成や、ガードリング付アバランシェ・フォトダ
イオードのイオン注入による高電界領域およびガードリ
ング構造の形成等である。
(Prior Art) In recent years, demand for light receiving elements as well as semiconductor lasers has increased in various fields, and research and development are being actively carried out in various places. Until now, various photodetector structures have been proposed, and some of them involve the use of p-oxides such as Zn during the manufacturing process.
There is a diffusion process of type impurities or an ion implantation process, and the quality of the process greatly influences the characteristics of the light receiving element. For example, p due to Zn diffusion in a normal pin photodiode.
These include the formation of an n-junction and the formation of a high electric field region and guard ring structure by ion implantation of an avalanche photodiode with a guard ring.

従来、このpinフォトダイオードは2例えばInoa
As/InP系を例にとると第4図に示すような工程で
製造されていた。
Conventionally, this pin photodiode is 2 eg Inoa
Taking the As/InP system as an example, it was manufactured using a process as shown in FIG.

(A)n”型InP基板1上にn型InP層(バッファ
ー層)2.n型I n G a A s層(受光層)3
を順次エピタキシャル成長する。
(A) n-type InP layer (buffer layer) 2. n-type InGaAs layer (light-receiving layer) 3 on n''-type InP substrate 1
are sequentially grown epitaxially.

(B)n型InGaAs層3上にSin、膜4を堆積し
、次にフォトリソグラフィー工程を用いて、受光部とな
る部分を化学的エツチングにより、窓をあける。
(B) A Sin film 4 is deposited on the n-type InGaAs layer 3, and then a window is opened by chemical etching in a portion that will become a light receiving portion using a photolithography process.

(C)ZnPzを拡散源として石英封管法によりZnの
選択拡散を行い、n型InGaAs層3中にpn接合を
形成する。
(C) Zn is selectively diffused by the quartz sealed tube method using ZnPz as a diffusion source to form a pn junction in the n-type InGaAs layer 3.

(D)Zn拡散領域5上に1反射防止膜6およびA u
 / Z nを用いてp型電極7を形成し、またn型I
nP基板1の裏面にAu/Snを用いてn型電極8を形
成する。
(D) Anti-reflection film 6 and A u on Zn diffusion region 5
/Zn to form a p-type electrode 7, and an n-type I
An n-type electrode 8 is formed on the back surface of the nP substrate 1 using Au/Sn.

このように、pin構造は、SiO2膜をマスクとして
石英封管法によるZn拡散で形成され、Zn拡散深さは
、拡散温度と時間により制御されていた。
In this way, the pin structure was formed by Zn diffusion using the quartz sealed tube method using the SiO2 film as a mask, and the Zn diffusion depth was controlled by the diffusion temperature and time.

また、ガードリング付アバランシェ・フォトダイオード
は、この場合InP系を例にとると第5図に示すような
工程で製造されていた。
Further, in this case, an InP-based avalanche photodiode with a guard ring was manufactured by a process as shown in FIG. 5.

(A)n+型InP基板1上にn型InP層(バッファ
ー層)2.n−型InP層(受光層)9を順次エピタキ
シャル成長する。
(A) n-type InP layer (buffer layer) 2. An n-type InP layer (light-receiving layer) 9 is epitaxially grown in sequence.

(B)フォトリソグラフィー工程によって形成したS 
i O、層4をマスクとしてSiのイオン注入10を行
い、n9型InP領域(高電界領域)11を形成する。
(B) S formed by photolithography process
Using the iO layer 4 as a mask, Si ion implantation 10 is performed to form an n9 type InP region (high electric field region) 11.

(C)(B)と同様に5102層4をマスクとしてZn
のイオン注入12を行い、P0型InP領域13を形成
する6 (D)pゝ型InP領域13上に、反射防止膜およびA
u/Znを用いてn型電極7を形成し、またn型InP
基板1の裏面にAu/Snを用いてn型電極8を形成す
る。
(C) Similarly to (B), using the 5102 layer 4 as a mask, Zn
6 (D) An anti-reflection film and an A
The n-type electrode 7 is formed using u/Zn, and the n-type InP
An n-type electrode 8 is formed on the back surface of the substrate 1 using Au/Sn.

なおこの場合、p0型InP領域13の形成にイオン注
入法を用いた場合について説明したが、前述したpin
フォトダイオードの場合と同様、石英封管法によるZn
拡散を用いても、同構造が得られる。
In this case, although the case where the ion implantation method was used to form the p0 type InP region 13 was explained, the above-mentioned pin
As in the case of photodiodes, Zn is manufactured using the quartz tube method.
The same structure can be obtained using diffusion.

このように、n0型InP領域(高電界領域)11およ
びp+型InP領域13は、二重のイオン注入法により
形成され、それぞれのn型層nP層9中での位置は、イ
オン注入の加速電圧およびその後のアニール工程の温度
9時間によって制御されていた。
In this way, the n0-type InP region (high electric field region) 11 and the p+-type InP region 13 are formed by a double ion implantation method, and their positions in the n-type layer nP layer 9 are determined by the accelerated ion implantation. The voltage and temperature of the subsequent annealing step were controlled for 9 hours.

(発明が解決しようとする課題) しかしながら上記のような方法で製造したpinフォト
ダイオードは、SiO□マスクを用いたZnの選択拡散
を行い、その拡散フロントをn型層 n G a A 
s中に位置させることによって、pin構造を形成する
ため、その製造工程が複雑となり、また再現性の点で問
題があった。また拡散は400〜500℃で行われるの
で、熱履歴が素子特性の劣化をもたらす1つの原因とな
っていた。
(Problems to be Solved by the Invention) However, in the pin photodiode manufactured by the method described above, Zn is selectively diffused using a SiO□ mask, and the diffusion front is connected to the n-type layer n Ga A
Since a pin structure is formed by locating the pin in S, the manufacturing process becomes complicated and there are problems in reproducibility. Further, since diffusion is performed at 400 to 500° C., thermal history has been one of the causes of deterioration of device characteristics.

またガードリング付アバランシェ・フォトダイオードの
場合、イオン注入法を用いて、n0型InP層(高電界
領域層)およびPI型型層P層を形成しているが、pi
nフォトダイオードのZn拡散工程と同様の問題が生じ
ている。
In addition, in the case of an avalanche photodiode with a guard ring, an n0 type InP layer (high electric field region layer) and a PI type layer P layer are formed using the ion implantation method.
Problems similar to those in the Zn diffusion process for n photodiodes have arisen.

本発明は、従来の欠点を解消し、従来のpinフォトダ
イオード構造を、1回のエピタキシャル成長で形成する
ことを目的とするものである。
The present invention aims to eliminate the drawbacks of the conventional technique and to form a conventional pin photodiode structure in a single epitaxial growth process.

(課題を解決するための手段) 本発明は、上記した従来の問題点を解消するため、第一
の伝導型を有する半導体基板上に、前記半導体基板上と
同伝導型のバッファー層、前記バッファー層上に前記半
導体基板と同伝導型の受光層を順次エピタキシャル成長
する工程と、前記受光層上に、n型およびp型不純物原
料を同時に供給し、かつ所望の部分に光照射を行いなが
ら半導体層をエピタキシャル成長する工程と前記半導体
層上に第1の電極層および反射防止膜、前記半導体基板
のバッファー層、受光層、半導体層が形成されていない
表面に第2の電極層を形成する工程とを用いてpinフ
ォトダイオードを製造するものである。
(Means for Solving the Problems) In order to solve the above-described conventional problems, the present invention provides a semiconductor substrate having a first conductivity type, a buffer layer having the same conductivity type as that on the semiconductor substrate, and a buffer layer having the same conductivity type as that on the semiconductor substrate. A step of sequentially epitaxially growing a light-receiving layer of the same conductivity type as the semiconductor substrate on the semiconductor substrate, and simultaneously supplying n-type and p-type impurity raw materials onto the light-receiving layer and irradiating the semiconductor layer with light to desired portions. and a step of forming a first electrode layer and an antireflection film on the semiconductor layer, and a second electrode layer on the surface of the semiconductor substrate on which the buffer layer, the light-receiving layer, and the semiconductor layer are not formed. This method is used to manufacture pin photodiodes.

また、本発明は第一の伝導型を有する半導体基板上に、
前記半導体基板上と同伝導型のバッファー層、前記バッ
ファー層上に前記半導体基板と同伝導型の受光層を順次
エピタキシャル成長する工程と、前記受光層上に、n型
およびp型不純物原料を同時に供給し、かつ所望の部分
に光照射を行いながら高電界領域層をエピタキシャル成
長する工程と、前記高電界領域層上に、前記n型および
p型不純物原料を同時に供給し、かつ前記光照射部の周
囲部を光照射しながら半導体層をエピタキシャル成長す
る工程と、前記半導体層上に第1の電極層、および反射
防止膜、前記半導体基板のバッファー層、受光層、高電
界領域層、半導体層が形成されていない表面に第2の電
極層を形成する工程とを用いて、pinフォトダイオー
ド、特にアバランシェ・フォトダイオードを製造するも
のである。
Further, the present invention provides, on a semiconductor substrate having a first conductivity type,
A step of sequentially epitaxially growing a buffer layer of the same conductivity type as on the semiconductor substrate, a light-receiving layer of the same conductivity type as the semiconductor substrate on the buffer layer, and simultaneously supplying n-type and p-type impurity raw materials onto the light-receiving layer. and a step of epitaxially growing a high electric field region layer while irradiating a desired portion with light, and simultaneously supplying the n-type and p-type impurity raw materials onto the high electric field region layer, and growing the high electric field region layer around the light irradiation portion. a step of epitaxially growing a semiconductor layer while irradiating the semiconductor layer with light, and forming a first electrode layer, an antireflection film, a buffer layer of the semiconductor substrate, a light receiving layer, a high electric field region layer, and a semiconductor layer on the semiconductor layer. A process of forming a second electrode layer on a non-containing surface is used to manufacture a pin photodiode, particularly an avalanche photodiode.

(作 用) この技術的手段による作用は次のようになる。(for production) The effect of this technical means is as follows.

エピタキシャル成長、特に有機金属熱分解法によるエピ
タキシャル成長において、熱分解効率よりも光分解効率
の方が大きいn型不純物原料と、光照射効果がほとんど
ないp型不純物原料とを同時に供給して、基板表面に光
を照射すると、光照射部でn型層、非照射部でP型層の
エピタキシャル成長が可能である。そこで、従来のpi
nフォトダイオード構造においてp型不純物拡散領域が
ある部分のエピタキシャル成長を行う場合、p型不純物
領域以外の部分に光を照射すると、光照射部はn型、非
照射部はp型となり、エピタキシャル成長終了時点で、
所望の部分にp壁領域が形成されている。従って、例え
ばpinフォトダイオードの場合は、最後のp壁領域を
含む層の成長の際、上記したn型およびp型不純物原料
を同時に供給して受光部となる部分以外の部分に光照射
を行うことにより、受光部にp型領域ができ、その結果
pn接合が形成される。
In epitaxial growth, especially epitaxial growth using organometallic pyrolysis, an n-type impurity raw material whose photolysis efficiency is higher than its thermal decomposition efficiency and a p-type impurity raw material which has almost no light irradiation effect are simultaneously supplied to the substrate surface. When light is irradiated, it is possible to epitaxially grow an n-type layer in the light-irradiated area and a p-type layer in the non-irradiated area. Therefore, the conventional pi
When epitaxially growing a part of an n-photodiode structure where there is a p-type impurity diffusion region, if light is irradiated to a part other than the p-type impurity region, the light-irradiated part becomes n-type and the non-irradiated part becomes p-type, and at the end of epitaxial growth. in,
A p-wall region is formed in a desired portion. Therefore, for example, in the case of a pin photodiode, when growing the final layer including the p-wall region, the above-mentioned n-type and p-type impurity raw materials are simultaneously supplied to irradiate light to the part other than the part that will become the light receiving part. As a result, a p-type region is formed in the light receiving portion, and as a result, a pn junction is formed.

また、光分解効率の方が大きいn型不純物原料だけを供
給して、基板表面に光を照射すると、光照射部でn9型
層、非照射部でn型層のエピタキシャル成長が可能であ
る。そこで従来のアバランシェ・フォトダイオード構造
において、n型のエピタキシャル層中にn0型領域(い
わゆる高電界領域)がある部分の成長の際、n+型領領
域形成する部分に光照射を行うと、光照射部はn0型。
Furthermore, by supplying only the n-type impurity raw material with higher photodecomposition efficiency and irradiating the substrate surface with light, it is possible to epitaxially grow an n9-type layer in the light-irradiated area and an n-type layer in the non-irradiated area. Therefore, in the conventional avalanche photodiode structure, when the part where the n0 type region (so-called high electric field region) is grown in the n type epitaxial layer, the part where the n+ type region will be formed is irradiated with light. The part is n0 type.

非照射部はn型となり、エピタキシャル成長終了時点で
所望の部分にn+型領領域高電界領域)が形成されてい
る。
The non-irradiated portion becomes n-type, and an n+ type region (high electric field region) is formed in a desired portion at the end of epitaxial growth.

(実施例) 本発明の実施例を第1図ないし第3図に基づいて説明す
る。
(Example) An example of the present invention will be described based on FIGS. 1 to 3.

本発明によるInGaAs/InP系pinフォトダイ
オードの製造工程を第1図に示す。この場合。
FIG. 1 shows the manufacturing process of an InGaAs/InP pin photodiode according to the present invention. in this case.

光励起有機金属熱分解気相成長法により、pinフォト
ダイオード構造のエピタキシャル成長を行なった。その
除用いたエピタキシャル成長装置の結晶成長室を第2図
に示す。同図において、1はInP基板、14はArF
エキシマレーザ光、16はIn(C,H,)、、Ga(
C2H,)3.Zn(CH3)、の供給口、17はAs
H3,PH318i(CH,)4(7)供給口、18は
排出口、19は光入射窓、20はカーボン製サセプタ、
21は加熱用の高周波コイル、22はマスクである。
A pin photodiode structure was epitaxially grown by photoexcited metal organic pyrolysis vapor phase growth. FIG. 2 shows the crystal growth chamber of the epitaxial growth apparatus used. In the same figure, 1 is an InP substrate, 14 is an ArF
Excimer laser light, 16 is In (C, H,), Ga (
C2H,)3. Zn(CH3), supply port 17 is As
H3, PH318i (CH,) 4 (7) supply port, 18 is discharge port, 19 is light entrance window, 20 is carbon susceptor,
21 is a high frequency coil for heating, and 22 is a mask.

In、Ga、As、Pのソース材料として、それぞれI
n(C2H,)、、Ga(C,H,)、、AsH,、P
H3を。
As source materials for In, Ga, As, and P, I
n(C2H,), ,Ga(C,H,), ,AsH,,P
H3.

またn型、n型不純物原料としてそれぞれ5i(CH3
)49 Zn(CH,)2を、またキャリアガスとして
H2を用いた。また照射用光源としてArFエキシマレ
ーザ光を用いた。そのときの各ガスは第1表の通りで、
例えばn型層nP層の場合はI n(C,Hs)aを0
.36. PH,を25. 5i(CH3)、を0.0
2の割合で混合しである(以下同様)。
In addition, 5i (CH3
)49 Zn(CH,)2 and H2 were used as carrier gas. Furthermore, ArF excimer laser light was used as the irradiation light source. Each gas at that time is as shown in Table 1,
For example, in the case of an n-type layer nP layer, I n (C, Hs) a is 0
.. 36. PH, 25. 5i(CH3), 0.0
It is mixed at a ratio of 2 (the same applies below).

最初、結晶成長室内のカーボン製サセプタ上に設置され
たn型InP基板1の温度を高周波誘導加熱により成長
温度600℃まで昇温する。なおこの際、InP基板表
面のサーマルダメージを防ぐためにPH,を25cc/
min供給した。そしてその後。
First, the temperature of the n-type InP substrate 1 placed on a carbon susceptor in a crystal growth chamber is raised to a growth temperature of 600° C. by high-frequency induction heating. At this time, in order to prevent thermal damage to the InP substrate surface, the pH was adjusted to 25cc/
Min was supplied. And after that.

第1図の(A)お゛よび(B)に示すように、n型層n
P層2、n型InGaAs層3を順次、第1表に示す成
長条件により成長を行い、pinフォトダイオード構造
を作成した。
As shown in FIG. 1 (A) and (B), the n-type layer n
A P layer 2 and an n-type InGaAs layer 3 were sequentially grown under the growth conditions shown in Table 1 to create a pin photodiode structure.

第1表 なおこの場合全流量としては6.5Q/win、成長時
の結晶成長室内圧としては100Torrである。また
前述したように2回目のn型層 n G a A s層
成長の際、n型不純物原料S i(CH3)4とp型不
純物JX料Zn(CHi)zとを同時に供給し、第1図
(B)に示すように、それらの供給開始と同時に、ドー
ナッツ状パターンのArFエキシマレーザ光14を1.
5w/a#のパワーで基板表面に対して垂直方向から照
射した。
Table 1 In this case, the total flow rate is 6.5 Q/win, and the pressure in the crystal growth chamber during growth is 100 Torr. Furthermore, as described above, during the second growth of the n-type nGaAs layer, the n-type impurity raw material Si(CH3)4 and the p-type impurity JX material Zn(CHi)z are simultaneously supplied, and the first As shown in Figure (B), at the same time as the supply starts, ArF excimer laser light 14 in a donut-shaped pattern is applied to 1.
Irradiation was performed perpendicularly to the substrate surface with a power of 5 W/a#.

この結果、非照射部にはキャリア濃度5X10”1−3
のp型層nGaAs領域15、照射部にはキャリア濃度
5X10”an−3のn型InGaAs領域が形成でき
、InGaAs層中にpn接合が形成された。
As a result, the carrier concentration in the non-irradiated area was 5×10”1-3
In the p-type layer nGaAs region 15, an n-type InGaAs region with a carrier concentration of 5×10”an-3 was formed in the irradiated portion, and a pn junction was formed in the InGaAs layer.

そして最後に、(C)に示すように、n−型InGaA
s層3上にSio2膜4を、またp型層nGaAs領域
15上に反射防止膜6およびAu/Znを用いてp型電
極M7を、またn型InP基板1の裏面にAu/Snを
用いてn型電極層8を形成した。
And finally, as shown in (C), n-type InGaA
A Sio2 film 4 is formed on the s-layer 3, a p-type electrode M7 is formed using an antireflection film 6 and Au/Zn on the p-type layer nGaAs region 15, and Au/Sn is formed on the back surface of the n-type InP substrate 1. Then, an n-type electrode layer 8 was formed.

以上のような本実施例によれば、1回のエピタキシャル
成長で、pinフォトダイオード構造が形成できた。そ
の結果、Zn拡散の工程が省略でき製造プロセスの簡略
化が大いにはがれた。またpn接合位置もエピタキシャ
ル成長によって制御できるので、その位置の再現性も向
上した。
According to this example as described above, a pin photodiode structure could be formed by one epitaxial growth. As a result, the process of Zn diffusion can be omitted, greatly simplifying the manufacturing process. Furthermore, since the pn junction position can be controlled by epitaxial growth, the reproducibility of the position has also been improved.

なおこの実施例の場合、n型層nP層2およびn型In
GaAs層3成長の場合、光照射は行なっていないが、
基板表面全体に光照射を行なっても、本実施例と同じp
inフォトダイオード構造が得られる。
In the case of this example, the n-type layer nP layer 2 and the n-type In
In the case of GaAs layer 3 growth, no light irradiation was performed, but
Even if the entire substrate surface is irradiated with light, the same p as in this example is obtained.
An in-photodiode structure is obtained.

次に本発明による第2の実施例、すなわちInP系ガー
ドリング付アバランシェ・フォトダイオードの場合につ
いて説明する。
Next, a second embodiment of the present invention, that is, a case of an InP-based avalanche photodiode with a guard ring will be described.

その製造工程を第3図に示す。なお第3図において、第
1図と同一部分には同一番号を付す。
The manufacturing process is shown in FIG. In FIG. 3, the same parts as in FIG. 1 are given the same numbers.

この場合、レーザ構造のエピタキシャル成長に用いた成
長方法、ソース材料、不純物原料、キャリアガス、およ
び、成長直前までの基板処理方法全流量、結晶成長室内
圧は第1の実施例の場合と全く同じである。
In this case, the growth method used for epitaxial growth of the laser structure, source material, impurity raw material, carrier gas, substrate processing method just before growth, total flow rate, and crystal growth chamber pressure are exactly the same as in the first embodiment. be.

最初、n1型InP基板1上にn型層nP層2、n−型
InP層9(3層)を順次、第2表に示す成長条件によ
り成長を行なった。
First, an n-type layer nP layer 2 and an n-type InP layer 9 (three layers) were sequentially grown on an n1-type InP substrate 1 under the growth conditions shown in Table 2.

第2表の見方は第1表と同様である。Table 2 can be viewed in the same way as Table 1.

この場合、2番目のn−型InP層成長の際、n型不純
物原料81(CH3)4を供給し、第3図(B)に示す
ようにその供給開始と同時に円形パターンのArFエキ
シマレーザ光14を照射した。また3番目のn−型In
P層成長の際、n型不純物原料5L(CH3)、とn型
不純物原料Zn(CHl)2とを同時に供給し、第3図
(C)に示すように、それらの供給開始と同時にドーナ
ッツ状パターン(2番目のn−型InP層成長時の照射
パターンの周囲部)のArFエキシマレーザ光14を照
射した。なお、ArFエキシマレーザ光の照射パワーは
、全て1.5w / tylであり、基板表面に対して
垂直方向から照射した。
In this case, when growing the second n-type InP layer, the n-type impurity raw material 81 (CH3) 4 is supplied, and at the same time as the supply starts, a circular pattern of ArF excimer laser light is applied as shown in FIG. 14 was irradiated. Also, the third n-type In
During the growth of the P layer, the n-type impurity raw material 5L (CH3) and the n-type impurity raw material Zn (CHl)2 are supplied at the same time, and as shown in FIG. ArF excimer laser light 14 was applied to the pattern (periphery of the irradiation pattern during growth of the second n-type InP layer). Note that the irradiation power of the ArF excimer laser light was 1.5 w/tyl in all cases, and the irradiation was performed from a direction perpendicular to the substrate surface.

この結果、2番目のn−型InP層の光照射部はキャリ
ア濃度I X 10” an−’のnI型InP領域1
1、非照射部はキャリア濃度I X 1016c+n−
3のn−型InP領域となり、また3番目のn−型In
P層の光照射部はI X 10” an−’のn−型I
nP領域、非照射部はI X 101san−’のp+
型InP領域13が形成できた。
As a result, the light irradiated part of the second n-type InP layer is an nI-type InP region 1 with a carrier concentration of I x 10''an-'.
1. The carrier concentration in the non-irradiated area is I x 1016c+n-
This becomes the third n-type InP region, and the third n-type InP region becomes the third n-type InP region.
The light irradiation part of the P layer is an n-type I of I x 10"an-'
nP region, non-irradiated part is p+ of I X 101san-'
A type InP region 13 was formed.

そして最後に、(D)に示すように、n−型InP層上
にSiO2膜4をp0型InP領域13上に反射防止膜
6をおよびAu/Znを用いてp型電極層7を、またn
1型InP基板1の裏面にAu/Snを用いてn型電極
層8をそれぞれ形成した。
Finally, as shown in (D), a SiO2 film 4 is formed on the n-type InP layer, an anti-reflection film 6 is formed on the p0-type InP region 13, and a p-type electrode layer 7 is formed using Au/Zn. n
An n-type electrode layer 8 was formed using Au/Sn on the back surface of the 1-type InP substrate 1, respectively.

以上のような本実施例において、1回のエピタキシャル
成長で、ガードリング付アバランシェ・フォトダイオー
ド構造が形成でき、製造プロセスの簡略化が大いに計ら
れた。またn”型InP領域(高電界領域)11の位置
および膜厚の再現性も大いに向上した。
In this embodiment as described above, an avalanche photodiode structure with a guard ring can be formed by one epitaxial growth, and the manufacturing process is greatly simplified. Furthermore, the reproducibility of the position and film thickness of the n'' type InP region (high electric field region) 11 was also greatly improved.

以上述べた実施例においては、pinフォトダイオード
の構造エピタキシャル成長に光励起有機金属熱分解気相
成長法を用いた場合について述べたが、本発明は光励起
M B E (Molecular BeamEpit
axy)法、光励起M OM B E (Metal 
OrganicMolecular Beam Epi
taxy)法、光励起VPE(Vapor Phase
 Epitaxy)法を用いた場合でも実現可能である
。また基板照射用光源としてArFエキシマレーザ光を
用いた場合について述べたが、本発明は、Arレーザ、
Co2レーザ、He−Cdレーザ、KrFやXeF等の
KrF以外のエキシマレーザを用いた場合でも実現可能
である。また以上述べた実施例はInGaAs/InP
系の場合について説明したが1本発明はInGaAsP
/InP系。
In the embodiments described above, a case has been described in which a photoexcited metal organic pyrolysis vapor phase epitaxy method is used for the structural epitaxial growth of a pin photodiode.
axy) method, optical excitation MOMBE (Metal
OrganicMolecular Beam Epi
(taxy) method, photoexcitation VPE (Vapor Phase)
This can also be achieved using the Epitaxy method. Furthermore, although the case has been described in which ArF excimer laser light is used as the light source for irradiating the substrate, the present invention also provides ArF excimer laser light,
It can also be realized using a Co2 laser, a He-Cd laser, or an excimer laser other than KrF, such as KrF or XeF. Further, the embodiments described above are InGaAs/InP
Although the case of InGaAsP was explained, the present invention is based on InGaAsP.
/InP type.

A Q G a A s / G a A s系等の他
のm−v族化合物半導体を用いた場合に用いることがで
きるばかりでな(SL、Ga更にZn5e’e’7.n
5Se等のn −vt族化合物半導体を用いた場合や、
CuGaSe、。
It can be used not only when using other m-v group compound semiconductors such as A
When using an n-vt group compound semiconductor such as 5Se,
CuGaSe.

Cu A (I S 、等のカルコパイライト型化合物
半導体を用いた場合にも適用可能である。またn型およ
びP型不純物の組合せとして1本実施例では、5L(C
H,)4とZn(CH3)、、を用いたが本発明は他の
熱分解効率よりも光分解効率の方が大きいn型不純物原
料と光照射効果のほとんどないn型不純物原料の組合わ
せの場合に用いることができるばかりでなく、光照射効
果のほとんどないn型不純物原料と熱分解効率よりも光
分解効率の方が大きいn型不純物原料の組合わせを用い
た場合にも適用可能である。また本実施例は、pinフ
ォトダイオードの場合であるが、フォトトランジスタ構
造や他の種々の受光素子構造に適用できることは言うま
でもない。
It is also applicable when using a chalcopyrite type compound semiconductor such as Cu A (I S ).In this example, 5L (C
H,)4 and Zn(CH3) were used, but the present invention combines an n-type impurity raw material with a higher photolysis efficiency than other thermal decomposition efficiencies and an n-type impurity raw material with almost no light irradiation effect. It is not only applicable when using a combination of an n-type impurity raw material that has almost no light irradiation effect and an n-type impurity raw material that has a higher photolysis efficiency than thermal decomposition efficiency. be. Further, although this embodiment is a case of a pin photodiode, it goes without saying that the present invention can be applied to a phototransistor structure and various other light receiving element structures.

(発明の効果) 本発明にかかる受光素子は、その受光素子構造のエピタ
キシャル成長の際、熱分解効率よりも光分解効率の方が
大きいn(p)型不純物原料と光照射効果のほとんどな
いp (n)型不純物原料とを同時にあるいは光分解効
率の方が大きいn型不純物原料のみを供給して、所望の
エピタキシャル層の所望の部分に光照射することにより
、同一のエピタキシャル層中にn型とp壁領域を、ある
いはn型領域とn+型領領域同時に形成したものである
(Effects of the Invention) During the epitaxial growth of the light-receiving element structure, the light-receiving element according to the present invention uses an n(p)-type impurity raw material whose photodecomposition efficiency is higher than its thermal decomposition efficiency, and p (which has almost no light irradiation effect). By supplying n-type impurity raw materials at the same time as n-type impurity raw materials or only supplying n-type impurity raw materials with higher photolysis efficiency and irradiating light onto a desired portion of a desired epitaxial layer, n-type and n-type impurity raw materials can be produced in the same epitaxial layer. A p-wall region or an n-type region and an n+-type region are formed simultaneously.

従って一回のエピタキシャル成長で、従来のZn拡散お
よびイオン注入領域形成後の構造と同一の構造が形成で
き、プロセスの簡略化が大いにはかれる。また、従来の
拡散およびイオン注入領域の位置が光照射の位置および
時間で制御可能なので、その位置精度、特にpn接合お
よび高電界領域の位置の向上がはかれる。
Therefore, the same structure as the conventional structure after forming Zn diffusion and ion implantation regions can be formed by one epitaxial growth, and the process can be greatly simplified. Further, since the positions of the conventional diffusion and ion implantation regions can be controlled by the position and time of light irradiation, the positional accuracy, especially the positions of the pn junction and the high electric field region, can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例におけるpinフォトダ
イオードの製造方法を示す工程断面図、第2図は本発明
の実施例においてエピタキシャル成長工程に用いた光励
起有機金属熱分解気相成長装置の結晶成長室の模式断面
図、第3図は本発明の第2の実施例におけるガードリン
グ付アバランシェ・フォトダイオードの製造方法を示す
工程断面図、第4図は従来のpinフォトダイオードの
製造方法を示す工程断面図、第5図は従来のガードリン
グ付アバランシェ・フォトダイオードの製造方法を示す
工程断面図である。 1− n型InP基板、 2− n型層nP層、 3−
 n型InGaAs層、4 ・・・S io、膜、 5
 ・・・ Zn拡散領域、 6・・・反射防止膜、 7
 ・・・ p型電極層、 8 ・・・n型電極層、9 
−  n−型InP層、10・・・Siのイオン注入、
11・・・ n0型InP領域、12・・・ Znのイ
オン注入、13・・・P0型InP領域、14− Ar
Fエキシマレーザ光、15・・・ p型丁n G a 
A s領域。 第1図 特許出願人 松下電器産業株式会社 二〜 第 4・ 図 第 図 第 図
FIG. 1 is a process cross-sectional view showing the method for manufacturing a pin photodiode in the first embodiment of the present invention, and FIG. 2 is a photo-excited organometallic pyrolysis vapor phase growth apparatus used in the epitaxial growth process in the embodiment of the present invention. A schematic cross-sectional view of a crystal growth chamber, FIG. 3 is a process cross-sectional view showing a method for manufacturing an avalanche photodiode with a guard ring in the second embodiment of the present invention, and FIG. 4 is a cross-sectional view showing a method for manufacturing a conventional pin photodiode. FIG. 5 is a process cross-sectional view showing a conventional method for manufacturing an avalanche photodiode with a guard ring. 1- n-type InP substrate, 2- n-type layer nP layer, 3-
n-type InGaAs layer, 4...S io, film, 5
...Zn diffusion region, 6...Antireflection film, 7
... p-type electrode layer, 8 ... n-type electrode layer, 9
- n-type InP layer, 10...Si ion implantation,
11... n0 type InP region, 12... Zn ion implantation, 13... P0 type InP region, 14- Ar
F excimer laser light, 15... p-type n Ga
A s area. Figure 1 Patent applicant: Matsushita Electric Industrial Co., Ltd. 2-4.

Claims (10)

【特許請求の範囲】[Claims] (1)第一の伝導型を有する半導体基板上に、前記半導
体基板上と同伝導型のバッファー層、前記バッファー層
上に前記半導体基板と同伝導型の受光層を順次エピタキ
シャル成長する工程と、前記受光層上に、n型およびp
型不純物原料を同時に供給し、かつ所望の部分に光照射
を行いながら半導体層をエピタキシャル成長する工程と
、前記半導体層上に第1の電極層および反射防止膜、前
記半導体基板のバッファー層、受光層、半導体層が形成
されていない表面に第2の電極層を形成する工程とを備
えてなることを特徴とするpinフォトダイオードの製
造方法。
(1) A step of sequentially epitaxially growing, on a semiconductor substrate having a first conductivity type, a buffer layer having the same conductivity type as that on the semiconductor substrate, and a light-receiving layer having the same conductivity type as the semiconductor substrate on the buffer layer; On the light-receiving layer, n-type and p-type
A step of epitaxially growing a semiconductor layer while simultaneously supplying a type impurity raw material and irradiating a desired portion with light, a first electrode layer and an antireflection film on the semiconductor layer, a buffer layer of the semiconductor substrate, and a light-receiving layer. A method for manufacturing a pin photodiode, comprising the steps of: forming a second electrode layer on a surface on which a semiconductor layer is not formed.
(2)エピタキシャル成長方法が、有機金属熱分解気相
成長法、あるいはハライド気相成長法、あるいはハイド
ライド気相成長法、あるいはガスソース分子線エピタキ
シー法、あるいは分子線エピタキシー法である請求項(
1)記載のpinフォトダイオードの製造方法。
(2) A claim in which the epitaxial growth method is metal-organic pyrolysis vapor phase epitaxy, halide vapor phase epitaxy, hydride vapor phase epitaxy, gas source molecular beam epitaxy, or molecular beam epitaxy (
1) Method for manufacturing the pin photodiode described above.
(3)光照射に用いる光源がエキシマレーザ、Arレー
ザ、Co_2レーザ、紫外線ランプである請求項(1)
記載のpinフォトダイオードの製造方法。
(3) Claim (1) wherein the light source used for light irradiation is an excimer laser, an Ar laser, a Co_2 laser, or an ultraviolet lamp.
A method of manufacturing the described pin photodiode.
(4)同時に供給するn型およびp型不純物原料のうち
少なくとも一方が、エピタキシャル成長温度で熱分解効
率よりも光分解効率の方が大きいものである請求項(1
)記載のpinフォトダイオードの製造方法。
(4) Claim (1) wherein at least one of the n-type and p-type impurity raw materials supplied at the same time has a photodecomposition efficiency higher than a thermal decomposition efficiency at the epitaxial growth temperature.
) A method for manufacturing a pin photodiode as described above.
(5)n型およびp型不純物原料が、それぞれSi(C
H_3)_4、Zn(CH_3)_2である請求項(4
)記載のpinフォトダイオードの製造方法。
(5) The n-type and p-type impurity raw materials are Si(C
Claim (4) which is H_3)_4, Zn(CH_3)_2
) A method for manufacturing a pin photodiode as described above.
(6)第一の伝導型を有する半導体基板上に、前記半導
体基板上と同伝導型のバッファー層、前記バッファー層
上に前記半導体基板と同伝導型の受光層を順次エピタキ
シャル成長する工程と、前記受光層上に、n型およびp
型不純物原料を同時に供給し、かつ所望の部分に光照射
を行いながら高電界領域層をエピタキシャル成長する工
程と、前記高電界領域層上に、前記n型およびp型不純
物原料を同時に供給し、かつ前記光照射部の周囲部を光
照射しながら半導体層をエピタキシャル成長する工程と
、前記半導体層上に第1の電極層および反射防止膜、前
記半導体基板のバッファー層、受光層、高電界領域層、
半導体層が形成されていない表面に第2の電極層を形成
する工程とを備えてなるpinフォトダイオードの製造
方法。
(6) epitaxially growing a buffer layer of the same conductivity type as the semiconductor substrate on a semiconductor substrate having a first conductivity type, and a light-receiving layer of the same conductivity type as the semiconductor substrate on the buffer layer; On the light-receiving layer, n-type and p-type
A step of epitaxially growing a high electric field region layer while simultaneously supplying a type impurity raw material and irradiating a desired portion with light, simultaneously supplying the n-type and p-type impurity raw materials on the high electric field region layer, and a step of epitaxially growing a semiconductor layer while irradiating a peripheral area of the light irradiation part with light, a first electrode layer and an antireflection film on the semiconductor layer, a buffer layer of the semiconductor substrate, a light receiving layer, a high electric field region layer,
A method for manufacturing a pin photodiode, comprising the step of forming a second electrode layer on a surface where a semiconductor layer is not formed.
(7)エピタキシャル成長方法が、有機金属熱分解気相
成長法、あるいはハライド気相成長法、あるいはハイド
ライド気相成長法、あるいはガスソース分子線エピタキ
シー法、あるいは分子線エピタキシー法である請求項(
6)記載のpinフォトダイオードの製造方法。
(7) A claim in which the epitaxial growth method is a metal-organic pyrolytic vapor phase epitaxy method, a halide vapor phase epitaxy method, a hydride vapor phase epitaxy method, a gas source molecular beam epitaxy method, or a molecular beam epitaxy method (
6) Method for manufacturing the pin photodiode described above.
(8)光照射に用いる光源がエキシマレーザ、Arレー
ザ、Co_2レーザ、紫外線ランプである請求項(6)
記載のpinフォトダイオードの製造方法。
(8) Claim (6) wherein the light source used for light irradiation is an excimer laser, an Ar laser, a Co_2 laser, or an ultraviolet lamp.
A method of manufacturing the described pin photodiode.
(9)同時に供給するn型およびp型不純物原料のうち
少なくとも一方が、エピタキシャル成長温度で熱分解効
率よりも光分解効率の方が大きいものである請求項(6
)記載のpinフォトダイオードの製造方法。
(9) At least one of the n-type and p-type impurity raw materials supplied at the same time has a photodecomposition efficiency higher than a thermal decomposition efficiency at the epitaxial growth temperature (6).
) A method for manufacturing a pin photodiode as described above.
(10)n型およびp型不純物原料が、それぞれSi(
CH_3)_4、Zn(CH_3)_2である請求項(
9)記載のpinフォトダイオードの製造方法。
(10) The n-type and p-type impurity raw materials are Si(
Claim (CH_3)_4, Zn(CH_3)_2
9) Method for manufacturing the pin photodiode described above.
JP63192854A 1988-08-03 1988-08-03 Manufacture of pin photodiode Pending JPH0242769A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63192854A JPH0242769A (en) 1988-08-03 1988-08-03 Manufacture of pin photodiode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63192854A JPH0242769A (en) 1988-08-03 1988-08-03 Manufacture of pin photodiode

Publications (1)

Publication Number Publication Date
JPH0242769A true JPH0242769A (en) 1990-02-13

Family

ID=16298076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63192854A Pending JPH0242769A (en) 1988-08-03 1988-08-03 Manufacture of pin photodiode

Country Status (1)

Country Link
JP (1) JPH0242769A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009125688A1 (en) * 2008-04-11 2009-10-15 ローム株式会社 Photoelectric conversion device, method for manufacturing the same, and solid state imaging device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009125688A1 (en) * 2008-04-11 2009-10-15 ローム株式会社 Photoelectric conversion device, method for manufacturing the same, and solid state imaging device
JP2009259872A (en) * 2008-04-11 2009-11-05 Rohm Co Ltd Photoelectric conversion device, method of manufacturing the same, and solid-state imaging device
US8592933B2 (en) 2008-04-11 2013-11-26 Rohm Co., Ltd. Photoelectric conversion device, fabrication method for the same, and solid state imaging device

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