JPH024175B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IF shift circuit for eliminating interference in a radio receiver.

[Conventional technology]

Conventionally, IF shift is performed by shifting (shifting) the received radio wave upward or downward from the center frequency of the intermediate frequency (IF) stage when an adjacent interfering radio wave enters the passband of the received radio wave. However, at the same time, the interference is removed by driving the interfering radio waves out of the IF passband, and in the case of standard AM waves and FM waves, this was done by moving the tuning knob to some extent.

However, when receiving CW (telegraph) or SSB, moving the tuning knob changes the pitch of the demodulated beat sound, so demodulation was performed while adjusting the pitch (BFO adjustment). .

[Problem to be solved by the invention]

In the conventional technology described above, each operation of tuning operation and pitch adjustment is required, so the 75S type receiver made by Collins in the United States was an early SSB receiver that dealt with this. The local oscillator that sets the tuning frequency and the adjustment shaft of the BFO are connected with a belt, and even if you change the IF frequency of the receiving board when the belt is variable, it will move by the same frequency in the same direction as the BFO frequency. Frequency correlation is something that can be made constant. However, since this receiver requires a mechanically sophisticated mechanism, there are almost no other examples of its use.

In addition, another classical method is the American method.
There is a 2B type receiver manufactured by Drake, and as shown in Figure 1, a four-stage LC tuning circuit is connected to capacitors 110 and 1.
11 and 112, and interlock the cores of coils 113, 114, 115, and 116 of the bandpass circuit, and finely adjust the cores to move the center frequency. The IF frequency and
Since the BFO frequency does not change, there is no need to worry about frequency deviation. However, due to the shape factor, an extremely low frequency of 50 kHz is used, making it difficult to apply to current circuits that use piezoelectric filters and the like at high intermediate frequencies.

Figure 2 is an example of a modern IF shift circuit.
The output of the pre-stage IF filter 120 (optional) is converted to the post-stage IF frequency by the mixer 122, and
The signal is input to a demodulator 124 through an IF filter 121 and an amplifier 125, and product detection is performed by injecting the oscillation frequency of the BFO 128. or,
The BFO frequency passes through buffer 126 and mixer 1
23 with the frequency of the fixed oscillator 127;
It is configured to inject into a mixer 122. Although a detailed explanation of the operation will be omitted, when the BFO frequency is changed, the IF that passes through the rear filter 121
The frequency changes (shifts) and matches the amount of change in the BFO frequency in the demodulator 124, so it is suitable for SSB.
This can be used for IF shift. However, the mixers 122 and 123 and the oscillator 127 are not necessarily necessary for purposes other than IF shifting, and in particular, increasing the number of mixer stages not only complicates the circuit, but also causes problems such as internal beat generation. be.

Figure 3 shows another example of an IF shift circuit.
The IF frequency is converted to an intermediate stage IF frequency by a mixer 133, further passed through an IF filter 131, and converted to a subsequent stage IF frequency by a mixer 134.
The signal passes through a filter 132 and is input to an amplifier and a demodulator (none of which are shown). On the other hand, mixer 1
The local frequencies of 33 and 134 are set by the same oscillator 135.
If the IF frequency of the intermediate stage changes as the oscillation frequency changes, the filter 131
The IF shift effect is performed in relation to the mixer 1.
33 and 134 are inverse frequency transforms, so the previous stage
The IF and the subsequent IF completely match, and there is no effect of shifting the IF. Also, filter 1
32 needs to have a wider band by an amount shifted from the filter 131.

For the reasons mentioned above, the introduction of an extra mixer into the signal circuit in this circuit is unavoidably disadvantageous in terms of noise and cross-modulation characteristics. When performing crystal control in each local oscillator, it is often thought that the frequency remains unchanged, but strictly speaking, it changes due to aging of the combined elements, so it is desirable to perform supplementary adjustment every few years.

[Means to solve the problem]

The present invention aims to solve the above-mentioned problems, and is aimed at solving the problems mentioned above.
The feature is that it uses the calculation, comparison judgment, and memory capacity of the CPU (referred to as the CPU) to correct aging changes by automatically calibrating the IF center frequency position each time it is used, without increasing the number of mixers that would have an adverse effect. a frequency marker oscillator controlled by a single reference oscillator, a first PLL-controlled
a local oscillator and a CPU, a first local oscillator whose frequency is controlled by the CPU, a second local oscillator for the intermediate frequency interstage mixer, and a third local oscillator for the demodulator.
It consists of a local oscillator (BFO), and the control data is stored in the CPU, and when starting the device, the first local oscillation frequency of PLL control is set based on the marker frequency according to the instructions of the CPU.
The second local oscillation frequency and the third local oscillation frequency are set to the center holding frequency of the intermediate frequency band filter, and from these set values, within the passband of the subsequent intermediate frequency band filter, the intermediate frequency is
The setting data of the second local oscillator and the third local oscillator for each step frequency in the case of shifting are stored, and the corresponding stored data is output according to the operation of the IF shift adjuster, and the setting data of the second local oscillator is By setting the oscillation frequency and the third local oscillation frequency, the IF of the wireless receiver that performs IF shift operation can be adjusted.
It is a shift circuit.

In addition, in the above, the PLL controlled local oscillator is
The local oscillator and the oscillator of the intermediate frequency interstage mixer are
The reason why the BFO of the local oscillator and demodulator is used as the third local oscillator is the minimum necessary configuration to meet the purpose of the present invention, which is to reduce the number of mixer stages in the circuit as much as possible. Even if the mixer and local oscillator used are added, the technical idea of the present invention is not affected by them.

〔Example〕

An embodiment of the present invention will be described based on the drawings. In FIG. 4, the receiving signal circuit includes a high frequency amplifier circuit 1, a first mixer 2, a first intermediate frequency filter 3, a second mixer 4, and a second intermediate frequency filter 5. , an intermediate frequency amplifier 6, and a demodulator 7 to obtain an audio output 71. In the above receiving circuit, the passband width is usually determined by the filter 5 as the main filter, and the filter 3 is set as an auxiliary filter to have a slightly wider band.

The local oscillator of the first mixer 2 is a PLL circuit (only the necessary limits are shown in the diagram) consisting of a VCO (voltage controlled oscillator) 8, a programmable frequency divider 9, and a phase comparator 10, and the reference frequency is The frequency of the reference oscillator 11 is divided by a frequency divider 12 and applied to the phase comparator 10. Also, this frequency is
Since it is often set to 100kHz or 1MHz, this is passed through the harmonic generator 13 as a marker frequency and is injected into the input circuit. This reference oscillator 11 also operates as a clock oscillator for the CPU 19, and the first, second, and third local oscillation frequencies are controlled by the CPU 19. In the end, all frequency settings are controlled by the single reference oscillator 11.
will be controlled by.

Furthermore, the first local oscillation frequency is CPU1
9, the digital data 91 is input to the programmable frequency divider 9 and set, and the second local oscillator 14 is
VXO (variable frequency crystal oscillator) and CPU
19 digital data 92A to the D/A converter 15
through the control voltage 92B to finely adjust the frequency. As a result, the relative position of the second intermediate frequency with respect to the filter 5 changes, so this data 9
2A is changed by an external regulator 21 to perform an IF shift operation. At this time, especially in the SSB reception mode, the third local oscillation frequency also needs to move in the same direction by exactly the same amount of change, so the third local oscillation frequency of the VXO is the digital data 93A output from the CPU 19. The tracking of the second local oscillation frequency and the third local oscillation frequency is controlled by the control voltage 93B passed through the /A converter 17.
It is executed by the software of the CPU 19.

For each circuit shown in FIG. 4, the software execution procedure necessary to implement the present invention is disclosed in claim 2. That is, (a) A voltage 92B obtained by D/A converting the output data 92A of the microcomputer 19 is applied so that the voltage is approximately at the center of the assumed variable range of the frequency control voltage of the second local oscillator 14.

(b) Output the marker operation output 94 from the CPU 19 to start the marker relay 20, turn on the normally-off contact 20A, and at the same time turn off the normally-on contact 20B connected to the output circuit,
Prevent beat output from being output to the speaker during calibration. Next, set the frequency setting number 91 for the first local oscillation frequency whose pre-stage intermediate frequency should match the center frequency of the filter 3 to the CPU 9.
1 and input to the programmable frequency divider 9, which is the frequency setting function of the PLL circuit.

(c) The demodulated beat sound 71 of the marker from the demodulator 7 is sent to the CPU 1 (through the waveform shaper 18 if necessary)
9, and the output 93B obtained by D/A converting the output 93A of the CPU 19 so that the frequency becomes 1500 Hz or the set frequency (depending on the device, it may be as wide as 1700 Hz) is output to the third local section. It is applied as a frequency control voltage to the oscillator 16, and data when the beat frequency 71 matches the set frequency is stored in the CPU 19.

(d) Next, change the second local oscillation frequency to the IF shift step frequency (the bandwidth of the subsequent filter is 3kHz).
Since it is before and after, if you shift the frequency in 10 steps between these steps, one step will be about 300Hz, so
IF shift steps start from 100Hz depending on the application
The control voltage 92B, which shifts the frequency by one unit (it is practical to set it in units of 500Hz), is applied to the CPU.
The data 92A output from 19 is given through the D/A converter 15, and the data at that time is
Stored in CPU 19.

(e) The CPU 19 changes the data 93A to move the third local oscillation frequency so that the beat sound 71 to be demodulated again becomes 1500 Hz or the set frequency, and stores the data at that time in the CPU 19.

(f) Hereinafter, the operations of the d and e terms are repeated while increasing or decreasing the data 92A in step frequency units of the IF shift, and the data immediately before the beat output 71 disappears is set as the end of the pass band.

(g) Furthermore, recall the data stored in terms b and c, change the local oscillation frequency of term d in the opposite direction, and send the data up to the end of the opposite passband to the CPU 19 in the same way as terms e and f. Remember.

(h) The frequency data closest to the arithmetic mean frequency of the upper and lower passband edge frequencies obtained in the previous section f and g is used as the IF center frequency data, and the stored value is rewritten in the data string for each frequency step of the IF shift. Organize.

(i) When the above is completed, the marker injection signal 94 stops,
Marker circuit contact 20A is separated and audio circuit contact 2
0B is connected and enters the receiving state. Also, by operating the IF shift adjuster 21, the values previously set in the CPU 19 by operating the d and e terms,
The stored data 92A and 93A are combined into a set and recalled at each step of the IF shift, thereby performing a desired IF shift.

〔Effect of the invention〕

According to the IF shift circuit of the present invention, each time it is used,
By automatically calibrating the IF center frequency position when the power is turned on, there is no need to correct aging changes in each circuit constant, and
By eliminating the mixer stage of the shift circuit that was necessary for the configuration of the IF shift circuit, there is an effect of preventing the generation of internal beats, and the absence of the mixer stage simplifies the circuit configuration. It is something that can be done.

In addition, this circuit has the effect of maintaining the correct frequency relationship simply by correcting the frequency of the reference oscillator, and the setting operations for each circuit can be performed without power supply.
Since this is done within a short time after the device is turned on and the device starts normal operation, it has the effect of not placing an unnecessary burden on the normal operation of the CPU.

[Brief explanation of drawings]

Figure 1 shows an example of the configuration of a conventional IF shift circuit.
Figure 2 shows an example of the configuration of an IF shift circuit currently in practical use, Figure 3 shows an example of another configuration of an IF shift circuit, Figure 4 shows an example of an implementation circuit of the present invention, and Figures 5 and 6 show a CPU. This is a flowchart explaining the operation. 1...High frequency amplifier, 2, 4, 122, 12
3,133,134……Mixa, 3,5,12
0,121,131,132...Filter, 7,
124...Demodulator, 8...VCO, 9...Programmable frequency divider, 10...Phase comparator, 11...
Reference oscillator, 12... Frequency divider, 13... Harmonic generator, 14, 16... VXO, 15, 17...
D/A converter, 18... Waveform shaper, 19...
CPU, 20-20B...Marker relay, 21
...IF shift adjuster, 22 ... Tuner, 110
~112...Coupling capacitor, 113-116...
...Band pass coil, 125, 126, 137...
...Amplifier, 127,128,135...Local oscillator.

Claims (1)

[Claims] 1. A frequency marker oscillator controlled by a single reference oscillator, a PLL-controlled first local oscillator, a microcomputer, a first local oscillator whose frequency is controlled by the microcomputer, and an intermediary frequency stage. It consists of a second local oscillator for the mixer and a third local oscillator (BFO) for the demodulator, and is configured to store control data in the microcomputer. When the first local oscillation frequency, second local oscillation frequency, and third local oscillation frequency of control are set to the center holding frequency of the intermediate frequency band filter, and the IF is shifted from the center frequency within the passband of the subsequent intermediate frequency band filter. Frequency setting data for the second local oscillator and the third local oscillator for each step frequency are stored in the microcomputer, and corresponding stored data is output according to the operation of the IF shift adjuster,
An IF shift circuit of a radio receiver that performs an IF shift operation by setting the second and third local oscillation frequencies. 2. The first local oscillation frequency at the time of starting the device,
The setting work of the second local oscillation frequency and the third local oscillation frequency, and the work of changing the second local oscillation frequency and the third local oscillation frequency associated with the operation of the IF shift adjuster, are performed when the power is turned on. A voltage obtained by D/A converting the output data of the microcomputer is applied so that the voltage is approximately at the center of the assumed variable range of the oscillation frequency control voltage of the oscillator. (b) Disconnect the antenna circuit, inject the marker output into the input, and output from the microcomputer a frequency setting value that will become the first local oscillation frequency whose pre-stage intermediate frequency should match the center frequency of the pre-stage band filter; Input to the frequency setting function of the PLL circuit. (c) Input the demodulated beat sound of the marker to the microcomputer, and apply the voltage obtained by D/A converting the output of the microcomputer so that the frequency becomes 1500Hz or the set frequency as the frequency control voltage of the third local oscillator. , the data when the frequencies match are stored in the microcomputer. (d) Next, a control voltage for shifting the second local oscillation frequency by one unit frequency of the step frequency of the IF shift is applied from the microcomputer through the D/A converter, and the data at that time is stored in the microcomputer. (e) Move the third local oscillation frequency so that the demodulated beat sound becomes 1500 Hz or the set frequency again, and store the data at that time in the microcomputer. (f) Hereafter, repeat the operation of the d and e terms while changing the step frequency unit of the IF shift,
The data immediately before the demodulated beat output disappears is defined as the passband edge. (g) Furthermore, recall the data of the d term and the c term, change the local oscillation frequency of the d term in the opposite direction to the d term, and retrieve the data up to the opposite end of the passband in the same way as the e term and f term. Stored in a microcomputer. (h) In the previous section, the frequency data closest to the arithmetic mean frequency of the upper and lower passband edge frequencies is
The stored values are reorganized as center frequency data into a data string for each frequency step of the IF shift. (i) After completing the above, turn off the marker injection, connect the antenna circuit and move to the receiving state, and collect one set of data that was set and stored by the operations in the d and e sections according to the IF shift adjustment. IF shift is performed by recalling as . The IF shift circuit according to claim 1, characterized in that the IF shift circuit operates according to the configurations described in each of the above sections.