JPH0241182U - - Google Patents
Info
- Publication number
- JPH0241182U JPH0241182U JP12076488U JP12076488U JPH0241182U JP H0241182 U JPH0241182 U JP H0241182U JP 12076488 U JP12076488 U JP 12076488U JP 12076488 U JP12076488 U JP 12076488U JP H0241182 U JPH0241182 U JP H0241182U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- frequency distribution
- stores
- final time
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000009825 accumulation Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Radar Systems Or Details Thereof (AREA)
Description
第1図はこの考案の一実施例による信号検出装
置を示すブロツク図、第2図はこの考案の他の実
施例を示すブロツク図、第3図は従来の信号検出
装置を示すブロツク図である。
図において、1は入力端子、2はパルス蓄積バ
ツフア、3は周波数出力線、4は到来パルス時刻
出力線、5は周波数頻度分布作成回路、6は周波
数頻度分布毎最終時刻作成回路、7は周波数頻度
分布メモリ、8は目標判定回路、9は同時入力判
定回路。なお、図中、同一符号は同一、又は相当
部分を示す。
FIG. 1 is a block diagram showing a signal detection device according to one embodiment of this invention, FIG. 2 is a block diagram showing another embodiment of this invention, and FIG. 3 is a block diagram showing a conventional signal detection device. . In the figure, 1 is an input terminal, 2 is a pulse accumulation buffer, 3 is a frequency output line, 4 is an arrival pulse time output line, 5 is a frequency frequency distribution creation circuit, 6 is a final time creation circuit for each frequency frequency distribution, and 7 is a frequency A frequency distribution memory, 8 a target determination circuit, and 9 a simultaneous input determination circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
検出装置において、到来パルスデータを蓄積する
蓄積バツフアと、規定の周波数幅毎に到来パルス
数をカウントし、このカウント値を記憶する周波
数頻度分布作成回路と、周波数頻度分布毎の到来
パルスの最終時刻を記憶する周波数頻度分布毎最
終時刻記憶回路と、カウント値と最終時刻を記憶
する周波数毎頻度分布メモリと、周波数頻度分布
毎の最終時刻から複数目標か否かを判定する目標
判定回路とを備えたことを特徴とする信号検出装
置。 A pulse signal detection device arriving from a radio wave emission source such as a radar includes an accumulation buffer that accumulates incoming pulse data, and a frequency frequency distribution creation circuit that counts the number of incoming pulses for each specified frequency width and stores this count value. , a final time memory circuit for each frequency frequency distribution that stores the final time of the arriving pulse for each frequency frequency distribution, a frequency distribution memory for each frequency that stores the count value and the final time, and a memory circuit for each frequency frequency distribution that stores the final time of the arriving pulse for each frequency frequency distribution, and a memory circuit for each frequency frequency distribution that stores the final time of the arriving pulse for each frequency distribution. A signal detection device comprising: a target determination circuit that determines whether or not a target is detected.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12076488U JPH0241182U (en) | 1988-09-14 | 1988-09-14 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12076488U JPH0241182U (en) | 1988-09-14 | 1988-09-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0241182U true JPH0241182U (en) | 1990-03-22 |
Family
ID=31367165
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12076488U Pending JPH0241182U (en) | 1988-09-14 | 1988-09-14 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0241182U (en) |
-
1988
- 1988-09-14 JP JP12076488U patent/JPH0241182U/ja active Pending
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