JPS5861553U - receiving device - Google Patents
receiving deviceInfo
- Publication number
- JPS5861553U JPS5861553U JP1981155329U JP15532981U JPS5861553U JP S5861553 U JPS5861553 U JP S5861553U JP 1981155329 U JP1981155329 U JP 1981155329U JP 15532981 U JP15532981 U JP 15532981U JP S5861553 U JPS5861553 U JP S5861553U
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit section
- section
- input signal
- oscillation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Circuits Of Receivers In General (AREA)
- Transceivers (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案に係る受信装置の一例を示す回路接続図
、第２図及び第３図は第１図に示された例の動作説明に
用いられる特性図及び波形図、第４図は本考案に係る受
信装置の一部分の第１図に示される例とは異なる他の例
を示す回路接続図である。
図中、３は中間周波増幅回路部、４は検波回路部、５は
音量調整回路部、６は低周波増幅回路部、７はスピーカ
、８は第一のレベル検出回路部、９及び１３はＮＯＲ回
路、１０はインバータ、１１は低周波発振回路部、１２
は第二のレベル検出回路部、１４は単安定マルチバイブ
レータ、Ｓ□は第一の切換スイッチ、Ｓ２は第二の切換
スイッチ、Ｄ０〜Ｄ５はダイオード、Ｔ１〜Ｔ６はトラ
ンジスタである。FIG. 1 is a circuit connection diagram showing an example of a receiving device according to the present invention, FIGS. 2 and 3 are characteristic diagrams and waveform diagrams used to explain the operation of the example shown in FIG. 1, and FIG. 2 is a circuit connection diagram showing another example different from the example shown in FIG. 1 of a part of the receiving device according to the present invention. FIG. In the figure, 3 is an intermediate frequency amplification circuit section, 4 is a detection circuit section, 5 is a volume adjustment circuit section, 6 is a low frequency amplification circuit section, 7 is a speaker, 8 is a first level detection circuit section, 9 and 13 are NOR circuit, 10 is an inverter, 11 is a low frequency oscillation circuit section, 12
14 is a monostable multivibrator, S□ is a first changeover switch, S2 is a second changeover switch, D0 to D5 are diodes, and T1 to T6 are transistors.
Claims (1)
的に採り得るようにされ、これらのいずれかの状態に於
いても入力信号に応じた出力を生ずる入力信号検出回路
部と、上記の２つの状態の夫々に於いて共通に動作せし
められる発振回路及び該発振回路部の出力に基ずく音を
発生せしめる出力部と、上記信号待機動作状態に於いて
、上記入力信号検出回路部の出力に基すいて所定レベル
以上の入力信号が到来したことを検知し、上記発振回路
部及び出力部を動作させて所定の放音をなさしめる第一
の制御回路部と、上記信号受信動作状態に於いて、上記
入力信号検出回路部の出力に基すいて所定レベル以上の
入力信号が到来しなくなったことを検知し、予め設定さ
れた時間だけ上記発振回路部及び出力部を動作させて所
定の放音をなさしめる第二の制御回路部とを具備して成
る受信装置。, an input signal detection circuit section that can selectively take a signal standby operating state and a signal receiving operating state, and generates an output according to the input signal even in either of these states; An oscillation circuit that is operated in common in each state and an output section that generates sound based on the output of the oscillation circuit section, and an output section that generates sound based on the output of the oscillation circuit section in the signal standby operation state, and an output section that generates sound based on the output of the input signal detection circuit section in the signal standby operation state. a first control circuit section that detects the arrival of an input signal of a predetermined level or higher and operates the oscillation circuit section and the output section to emit a predetermined sound; , detecting that an input signal of a predetermined level or higher has ceased to arrive based on the output of the input signal detection circuit section, and operating the oscillation circuit section and output section for a preset time to emit a predetermined sound. A receiving device comprising: a second control circuit section that performs the following operations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981155329U JPS5861553U (en) | 1981-10-19 | 1981-10-19 | receiving device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981155329U JPS5861553U (en) | 1981-10-19 | 1981-10-19 | receiving device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5861553U true JPS5861553U (en) | 1983-04-25 |
| JPS6225001Y2 JPS6225001Y2 (en) | 1987-06-26 |
Family
ID=29947907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1981155329U Granted JPS5861553U (en) | 1981-10-19 | 1981-10-19 | receiving device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5861553U (en) |
-
1981
- 1981-10-19 JP JP1981155329U patent/JPS5861553U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6225001Y2 (en) | 1987-06-26 |
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