JPH024024B2 - - Google Patents

Info

Publication number
JPH024024B2
JPH024024B2 JP56119916A JP11991681A JPH024024B2 JP H024024 B2 JPH024024 B2 JP H024024B2 JP 56119916 A JP56119916 A JP 56119916A JP 11991681 A JP11991681 A JP 11991681A JP H024024 B2 JPH024024 B2 JP H024024B2
Authority
JP
Japan
Prior art keywords
address
cpu
signal
main memory
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56119916A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5819966A (ja
Inventor
Kenichi Oonishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP56119916A priority Critical patent/JPS5819966A/ja
Publication of JPS5819966A publication Critical patent/JPS5819966A/ja
Publication of JPH024024B2 publication Critical patent/JPH024024B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP56119916A 1981-07-30 1981-07-30 Ｄｍａ転送方式 Granted JPS5819966A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56119916A JPS5819966A (ja) 1981-07-30 1981-07-30 Ｄｍａ転送方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56119916A JPS5819966A (ja) 1981-07-30 1981-07-30 Ｄｍａ転送方式

Publications (2)

Publication Number Publication Date
JPS5819966A JPS5819966A (ja) 1983-02-05
JPH024024B2 true JPH024024B2 (enrdf_load_html_response) 1990-01-25

Family

ID=14773357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56119916A Granted JPS5819966A (ja) 1981-07-30 1981-07-30 Ｄｍａ転送方式

Country Status (1)

Country Link
JP (1) JPS5819966A (enrdf_load_html_response)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60258670A (ja) * 1984-06-05 1985-12-20 Fanuc Ltd デ−タ授受方法

Also Published As

Publication number Publication date
JPS5819966A (ja) 1983-02-05

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