JPH023966A - Semiconductor device - Google Patents

Abstract

PURPOSE:To simplify a metallic wiring processing by a method wherein metal films for power supply wiring use, which can be used in common to any application, are formed in advance and are electrically connected with a well through a contact hole in an insulating film. CONSTITUTION:A first insulating film 3, in which a contact hole to a well is formed, is formed on the surface of a semiconductor chip 1 and metal films 4 and 5 constituting a power supply wiring are formed on the film 3 in a cross- fingered shape and are electrically connected to the well through the contact hole in the film 3. Moreover, a second insulating film is uniformly formed on the first insulating film 3 and the films 4 and 5. By this constitution, as the films 4 and 5 for power supply wiring use are formed in advance, a metallic wiring processing after the films 4 and 5 meet each application is simplified and the number of sheets of masks to be needed is reduced, and at the same time, the following metallic wiring processing can be executed in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a semiconductor device such as a universalized gate array, which is subjected to wiring processing later depending on the application.

(Prior Art) Semiconductor devices such as verticalized gate arrays have been widely known. In this gate array, semiconductor wafers are mass-produced with the manufacturing process up to the metal wiring completed, and the desired circuit is realized by adding metal wiring according to the user's application.

(Problem to be Solved by the Invention) In the conventional gate array described above, multilayer wiring technology is generally adopted for metal wiring processing to configure a desired circuit, but masks are required depending on the number of layers. be. Two-layer aluminum wiring, which is currently the mainstream, requires at least five masks, and three-layer aluminum wiring requires seven masks. Since a large number of masks must be prepared for each application, a large amount of money is required for the masks, resulting in high costs. In addition, all metal wiring is processed according to the application, which increases manufacturing time and makes it difficult to meet urgent demands.

The purpose of the present invention is to provide a semiconductor device that eliminates the above-mentioned conventional drawbacks, reduces the number of masks used, reduces costs, and allows metal wiring processing to be performed in a short time according to the application. This is what I am trying to do.

(Means for Solving the Problems) A semiconductor device according to the present invention includes a semiconductor substrate having a large number of wells and semiconductor regions formed therein, and a first insulator formed on the surface of the semiconductor substrate and having a contact hole for the wells. at least two metal films for power wiring formed on the first insulating film according to a predetermined pattern and electrically connected to the well via the contact hole; and these metal films for power wiring. and a second insulating film uniformly formed on the first insulating film.

(Function) In the present invention, all metal wiring processing is not performed according to the application, but the first layer of metal wiring is formed in advance. In this case, the first layer of metal wiring formed in advance is a metal film for power supply wiring that is commonly formed for any application, except for those that are selectively formed according to each application. put.

Further, in the embodiments to be described later, a metal film for signal wiring electrically connected to various semiconductor regions and gate electrodes formed on the semiconductor substrate is also formed in advance. Since the first layer of metal film is applied in this way, subsequent metal wiring processing according to each application is extremely simple, the number of masks required is significantly reduced, and subsequent metal wiring processing can be completed in a short period of time. It can be done with Furthermore, since the metal film for power wiring can be present over almost the entire surface of the chip, the current density is reduced and electromigration can be prevented, and it also functions as an electromagnetic shield, reducing the effects of noise. It is possible to realize a semiconductor device that is less susceptible to susceptibility.

(Embodiment) FIG. 1 is a diagrammatic plan view showing the basic configuration of a semiconductor device of the present invention. A large number of cells 2 are arranged in a matrix in a semiconductor chip 1 . semiconductor chip 1
A first insulating film 3 is uniformly formed on the surface of the insulating film 3, and metal films 4 and 5 constituting the power supply wiring are formed on this insulating film.
is formed in an interdigital shape (interdigital shape). One metal film 4 for power supply wiring is connected to power supply voltage VSS, and the other metal film 5 for N source wiring is connected to power supply voltage VSS. Since it is connected to , hereafter ν,.

membrane and V. It will also be abbreviated as 0 film.

As shown in FIG. 1, the VSS film 4 and V. Since the zero film 5 is of an interdigital type, it covers almost the entire surface of the semiconductor chip 1. therefore,
These metal films 4 and 5 also function as an electromagnetic shield, making them less susceptible to noise. Although not shown in FIG. 1, a second insulating film is uniformly formed on the first insulating film 3 and the metal film 4.5.

FIG. 2 shows in detail the structure of one cell 11 of a gate array which is an embodiment of a semiconductor device according to the present invention, and FIG. 3 is a cross section taken along line A-A in FIG. It is a diagram. This example has a six-transistor structure including four large transistors and two small transistors. Metal film 12 for power supply wiring connected to VSS and V
The power wiring metal films 13 connected to the OIDs are alternately formed so as to cover almost the entire surface of the semiconductor chip, similar to that shown in FIG. Inside the large opening 12a formed in the VSS film 12, source contact films 14 of two large npn type transistors are formed. 15 and a common drain contact film 16 are formed, and a source and drain contact film 17 of an npn type small transistor is formed in the small opening 12b (actually continuous with the opening 12a).
and 18. The VSS film 12 further includes source and drain contact films 17 for small transistors.
Small openings 12c and 12 above and below 18
d, and gate contact films 19 and 20 of small transistors are formed in these openings. Furthermore, VS
Gate contact films 21.22 and 23.24 of two large transistors are formed above and below the large opening in the S film 12. The van film 13 is also constructed in the same manner as the two VSS films. That is, the source and drain contact films 31, 32 and 33 of the two large transistors are formed in the large opening 13a, and the source and drain contact films 34 and 35 of the small transistor are formed in the large opening 13a.
are formed in the small opening 13b, the gate contact films 36 and 37 of the small transistor are formed in the openings 13C and 13d, and the gate contact films 38, 39 and 40.41 of the large transistor are formed outside the vDn film. Form.

As shown in the cross-sectional view of FIG. 3, an n-type well 52 is formed on the surface of a p-type semiconductor substrate 51 under the van film 13,
A number of p-type heads are formed within this well.

On the other hand, under the Vss film 12, a large number of n-type regions are formed in a p-type well (or the semiconductor substrate itself). As shown in FIG. 2, the VSS film 12 has a well contact 53
and 54 to the p-type well, and the n-type well 5 is connected to the n-type well 5 by the 3 well contacts 55 and 56 on the vno film 1.
Connected to 2. As shown in FIG.
1, a first insulating film 57 is formed on the surface of the metal film 12.13 for power wiring and the metal film 14-24.1 for signal wiring.
31 to 41 are formed on this first insulating film. Further, these metal films are connected to the lower semiconductor region and the gate electrode through contact holes formed in the first insulating film 57. Furthermore, as shown in FIG. 3, a second insulating film 58 is uniformly formed on the metal film to prevent deterioration of the metal film due to oxidation.

As described above, in the present invention, the first insulating film 57 is formed on the surface of the semiconductor substrate 51 on which various necessary semiconductor regions are formed and a gate electrode film is formed via a gate oxide film.
A VSS film 12 and a VDD film 1 are formed thereon and connected to the well through a contact hole formed in the first insulating film.
Metal films 14 to 24 for signal wiring are connected to the semiconductor region and the gate electrode through contact holes formed in the first insulating film while forming metal films for power supply wiring such as No. 3, etc.; 31 to 4;
1 and then a second insulating film 58 is uniformly formed thereon to form a gate array. To configure a desired circuit according to each application, contact holes with a desired pattern are formed in the second insulating film, and one or two layers of metal film are connected to the required signal wiring metal film. Just form it. In this case, since the metal film for power supply wiring and the metal film for signal wiring are formed in advance, it becomes possible to process more wiring, improving the gate usage rate, and reducing the number of masks that need to be prepared compared to conventional methods. It is possible to reduce the cost significantly compared to the conventional one, thus reducing the cost. Further, since the wiring processing to be performed later can be performed in a short time, it is possible to sufficiently deal with urgent demands.

In addition, in the present invention, contact films for all transistors are formed in advance, so some contact films are not used when actually configuring the circuit, but the gate usage rate is as high as 50 to 75%. , most of the contact film will be used, and no major waste will occur.

The present invention is not limited to the embodiments described above, but can be modified and modified in many ways.

For example, in the above example, the gate array is of a six-transistor type, but a gate array of other configurations may be used. Furthermore, in the above example, van is used as the metal film for power supply wiring.
Although the film and the VSS film are formed, other metal films for power supply wiring can also be formed.

(Effects of the Invention) In the double semiconductor device of the present invention, the metal film for power supply wiring connected to the well of the semiconductor substrate or the signal film connected to the metal film for power supply wiring and various semiconductor regions and gate electrode films. Since the metal film for wiring is formed on the first insulating film according to a predetermined pattern, and the second insulating film is uniformly formed on the first insulating film, it is very easy to process the wiring according to each application, and the number of sheets can be reduced. This can be done in a short time using a mask. That is, the mask cost required for the first layer metal wiring can be shared through mass production, and the cost can be reduced. Further, since a wide metal film for power supply wiring can be formed over almost the entire surface of the semiconductor chip, electromigration can be prevented and a circuit that is less susceptible to noise can be constructed.

[Brief explanation of the drawing]

FIG. 1 is a diagrammatic plan view showing the basic configuration of a semiconductor device according to the present invention, FIG. 2 is a plan view showing the structure of a cell of an embodiment of a gate array according to the present invention, and FIG. - It is a sectional view cut along the A line. ■...Semiconductor chip 2...Cell 3...1st
Insulating film 4.5... Metal film for power wiring 11... Cell 12.13... Metal film for power wiring 14-24. 31-41... Metal film for signal wiring 51... Semiconductor substrate 58...Second insulating film

Claims (1)

[Scope of Claims] 1. A semiconductor substrate in which a large number of wells and semiconductor regions are formed, a first insulating film formed on the surface of this semiconductor substrate and in which a contact hole for the well is formed, and this first insulating film. at least two metal films for power supply wiring formed on the top according to a predetermined pattern and electrically connected to the well through the contact hole, and on these metal films for power supply wiring and the first insulating film. A semiconductor device comprising a second insulating film uniformly formed. 2. A gate electrode is formed on the semiconductor substrate via a gate insulating film, a contact hole for the semiconductor region and the gate electrode is also formed in the first insulating film, and a first
2. The semiconductor device according to claim 1, further comprising a plurality of signal wiring metal films electrically connected to the semiconductor region and the gate electrode via these contact holes.