JPH0239132B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an oscillation circuit, and its purpose is to use a C-MOS element and to be constructed with a small time-limiting capacitor, making it small and inexpensive, and to achieve the low current consumption that C-MOS has. An object of the present invention is to provide an oscillation circuit that maintains a noise margin and has excellent temperature characteristics. Conventionally, oscillation circuits using inverters have been used, but in order to obtain low frequencies, this requires a non-polar capacitor of several μF, which has the disadvantage of increasing the size. Also, if the oscillation frequency adjustment scale and knob are external, for example, when the main volume is set to full scale, there will be variations in the main volume, capacitor, and IC, so the full scale indicated value will be different. Therefore, an internal fine adjustment volume is provided, but since this internal fine adjustment volume is connected in series or parallel with the main volume, it has the disadvantage that linearity deviates. The present invention has been made in view of this point, and will be explained in detail below with reference to Examples. In FIG. 1, 1 is a first differential circuit, 2 is a second differential circuit, and one input terminal is connected to a first differential circuit.
The reference voltage circuit 3 and the second reference voltage circuit 4 are connected, and the other input terminals are connected to each other, and a time-limiting capacitor C _T is connected to this connection point,
Further, a constant current bias circuit 5 for driving constant current MOS transistors of the differential circuits is connected to each differential circuit. 6 is an R-S type flip-flop circuit, which inputs the outputs of the first differential circuit and the second differential circuit 2, and sends the output to the time-limiting resistor R _T
The signal is inputted to the other input terminal of the first differential circuit 1 and the second differential circuit 2 via the RS flip-flop circuit 6, and an oscillation output is obtained from the RS type flip-flop circuit 6. In this oscillation circuit, when the power is turned on, the second
Since the reference voltage Vb of the differential circuit 2 is high, the output logic level of the second differential circuit 2 becomes H level as shown in FIG. It becomes H level like this. Therefore, charging of the time-limiting capacitor _CT starts via the time-limiting resistor _RT . When the charging voltage of the time-limiting capacitor C _T exceeds Vb, the output of the second differential circuit 2 becomes L level. As charging progresses further and the charging voltage of the time-limiting capacitor _CT exceeds the reference voltage Va as shown in Figure 2a, the output logic level of the first differential circuit 1 changes as shown in Figure 2b, and this is reversed. The H level is input to the RS type flip-flop circuit 6, and its output becomes the L level. Since the output is at the L level, the charge in the time-limiting capacitor C _T is discharged via the time-limiting resistor _RT . Then, when the input of the first differential circuit 1 becomes lower than the reference voltage Va, the first output level returns to the original level. The discharge of the time-limiting capacitor C _T progresses, and the terminal voltage becomes the reference voltage Vb.
When the voltage drops, the output level of the second differential circuit 2 becomes H level again, the output level of the RS type flip-flop circuit 6 also becomes H level, and the time limit capacitor C _T becomes charged again. When the terminal voltage exceeds the reference voltage Vb, the output of the second differential circuit 2 becomes L level. By repeating such operations, an oscillation output is obtained from the RS type flip-flop circuit 6. By the way, the first differential circuit 1 and the second differential circuit 2 are each constructed using enhancement type MOS transistors as shown in FIGS. 3a and 3b. That is, the first P channel MOS transistor (PMOS transistor) of the first differential circuit 1
A series circuit of PMOS ₁ and the _first N-channel MOS transistor (NMOS transistor)
2P channel MOS transistor PMOS ₂ and 2nd N
A third N-channel MOS transistor NMOS ₃ is connected in series to a series circuit of N-channel MOS transistors NMOS ₂ connected in parallel.
The gate of PMOS ₁ is connected to the gate and source of PMOS ₂ , and the gate of NMOS ₃ is connected to a constant current bias circuit 5, the gate of NMOS ₂ is connected to the power supply Va, and the gate of NMOS ₁ is connected to a time-limited gate. Connect to capacitor C _T. On the other hand, the second differential circuit 2 has a fifth P channel as shown in FIG. 3b.
3rd P channel in MOS transistor PMOS ₅
MOS transistor PMOS ₃ and 4th N-channel
Series circuit of MOS transistor NMOS ₄ , fourth P channel MOS transistor PMOS ₄ and fifth N
In addition to connecting the channel MOS transistor NMOS ₅ in parallel with the series circuit, the gate and source of NMOS ₄ are connected to the gate of NMOS ₅ , and the gate of PMOS ₅ is further connected to the constant current bias circuit 5. , connect the gate of PMOS ₄ to the time-limiting capacitor _CT , and connect the gate of PMOS ₃ to the reference voltage Vb. By the way, the gate width and channel width W of the above-mentioned MOS transistor are expressed by the following three groups S, M, and L.
Select. However, in this case, the length L is 8μ.

[Table] When the MOS transistors selected in this way were combined and the temperature characteristics at 60°C compared to room temperature were investigated, the following results were obtained.

【table】

[Table] From the above, if the gate width W is selected as S, the temperature characteristics will be poor and it cannot be used. Further, when M or L is selected, the absolute value itself is small and the temperature characteristics are excellent, but when L is selected, the chip area becomes large, resulting in high cost. Therefore, in conclusion, the gate width W of the MOS transistor of the first differential circuit 1 is set to M (however, NMOS ₂ L), and the gate width W of the second differential circuit 2 is set to M. By using one range, the temperature characteristics will be (-0.3%) + (0.07%) = (-0.23%) from the above table, and an oscillation circuit with stable temperature characteristics can be obtained. The reason for such stable temperature characteristics is as follows. In differential amplifiers, when the circuit configuration is the same, load capacitance such as wiring capacitance is approximately constant regardless of the size of the MOS transistor. On the other hand, M.O.S.
The drain capacitance and gate capacitance of a transistor are
It increases or decreases in proportion to the size of the MOS transistor,
Furthermore, the drive capacity (current) of the MOS transistor also increases or decreases in the same way. Therefore, if the wiring capacitance, etc. is zero, when the size of the MOS transistor is large, the load will be large, but the driving capacity will also be large, while when it is small, both will be small, and the response of the differential amplifier will eventually be The temperature characteristic of speed is a constant value. However, in a differential amplifier, wiring capacitance actually exists. The ratio of the wiring capacitance to the drain capacitance approaches zero as the size of the MOS transistor increases, and the temperature characteristics become optimal. Conversely, as the size of the MOS transistor becomes smaller,
The ratio of wiring capacitance to drain capacitance becomes large, and the rate of change in response speed at high temperatures becomes large. That is, as the size of the MOS transistor increases, the change in temperature characteristics becomes more consistent. Although the above description has been made for the case where the length of L is 8 μm, similar effects can be obtained even when the length of L is 4 μm or 6 μm by setting the gate width W ₁ to be the same W/L as described above. Here, the selection of 4 μm, 6 μm, and 8 μm was used because it was a standard process, so it is thought that the same effect can be obtained with 5 μm and 7 μm, which are in between. Also, PMOS ₁ ,
As PMOS ₂ , for example, the gate width W is 100 μm included in the group M, ±25%, that is, 100 μm,
When three types, 75 μm and 125 μm, were used and their characteristics were examined, equivalent properties were obtained in all cases. Incidentally, FIG. 4 is a specific circuit diagram of the present invention. As mentioned above, in the present invention, the oscillation circuit is constructed using a differential circuit composed of C-MOS transistors, so unlike an oscillation circuit using an inverter, a large non-polar capacitor of several μF is not required. Therefore, there is an advantage that the oscillation circuit can be formed in a small size. Furthermore, by using the C-MOS transistor in this manner, the advantages of the C-MOS transistor, such as low current consumption and high noise margin, can be maintained. Furthermore, P channel MOS transistors and N channel MOS transistors constituting the first and second differential circuits
Gate size ratio W/L and gate length L that provide good temperature characteristics of channel MOS transistors
is specified to a predetermined size, it is possible to minimize the possibility that the output state of the differential circuit fluctuates depending on the temperature and the oscillation frequency shifts, which means that the temperature characteristics of the differential circuit can be stabilized. can. Moreover, if the temperature characteristics of the differential circuit are stabilized in this way, there is an advantage that adjustments for improving other temperature characteristics can be easily made. In other words, there is no need to provide an internal fine-tuning volume to adjust the deviation in the oscillation frequency, and the variation component due to the output of the differential circuit has almost no effect on the adjustment of the temperature characteristics. This has the advantage that temperature compensation for the capacitor can be easily performed.

[Brief explanation of drawings]

Figure 1 is a basic circuit diagram of an embodiment of the present invention, Figure 2 is a basic circuit diagram of an embodiment of the present invention.
Figures a to d are voltage waveform diagrams of the same main parts as above, Figure 3 a, b
are circuit diagrams of the first differential circuit and second differential circuit, respectively, and FIG. 4 is a specific circuit diagram of the present invention. 1...First differential circuit, 2...Second differential circuit, 3
...First reference voltage circuit, 4...Second reference voltage circuit, 5...Constant current bias circuit, 6...R-S type flip-flop circuit, R _T ...Time limit resistor, C _T ...Time limit capacitor, POMS ₁ ...First P-channel MOS transistor, PMOS ₂ ... second P-channel MOS transistor, PMOS 3 ... third P-channel MOS transistor, PMOS ₄ ... _fourth P-channel MOS transistor, PMOS ₅ ... fifth P-channel MOS transistor, NMOS ₁ ...first N-channel MOS transistor, NMOS ₂ ...second N-channel MOS
Transistor, NMOS ₃ ...Third N-channel
MOS transistor, NMOS ₄ ...Fourth N-channel MOS transistor, NMOS ₅ ...Fifth N-channel MOS transistor.

Claims (1)

[Claims] 1 Connect a reference voltage circuit to one input terminal of the first differential circuit and the second differential circuit, connect the other input terminals to each other, connect a time-limiting capacitor, and For current
Constant current bias circuits for driving MOS transistors are connected to first and second differential circuits, respectively, and outputs of the first differential circuit and second differential circuit are input to an R-S type flip-flop circuit. an oscillation circuit in which the output of an RS type flip-flop circuit is inputted to the other input terminal of the first differential circuit and the second differential circuit via a time-limiting resistor; A _series circuit of an enhancement type first P-channel MOS transistor and a first N-channel MOS transistor, and a series circuit of a second P-channel MOS transistor and a second N-channel MOS transistor are connected in parallel to the power supply V DD. A third channel for those who
Connect MOS transistors in series and connect the other one to the power supply V _SS
the gate of the first P-channel MOS transistor and the gate and source of the second P-channel MOS transistor are connected to each other, and the first and second P-channel MOS transistors are connected to
MOS transistor gate size W/L ratio
12.5 times ±25%, L length is 4μm, 6μm or 8μm, first, second and third N-channel MOS
The transistor gate size W/L ratio is 10 times ±25%, 20 times ±25% and 8 times ±25%, L
The length of 4μm, 6μm or 8μm respectively,
A differential circuit is connected to the power supply V _DD via a fifth P-channel MOS transistor of an enhancement type, and a series circuit of a third P-channel MOS transistor and a fourth N-channel MOS transistor, and a fourth P-channel MOS transistor. 5th N
Connect one end of the channel MOS transistor connected in parallel with the series circuit, and connect the other end to the power supply.
V _SS and connects the gate and drain of the fourth N-channel MOS transistor to the gate of the fifth N-channel MOS transistor, and the gates of the third, fourth, and fifth P-channel MOS transistors. The size W/L ratio is 20 times ± 25%, 20 times ± 25% and 6 times ±
25%, L length is 4 μm, 6 μm or 8 μm, and the gate size W/L ratio of the fourth and fifth N-channel MOS transistors is respectively 10 times ±25%, L
An oscillation circuit characterized in that the length of the circuit is 4 μm, 6 μm or 8 μm.