JPH0236280Y2 - - Google Patents
Info
- Publication number
- JPH0236280Y2 JPH0236280Y2 JP1983033581U JP3358183U JPH0236280Y2 JP H0236280 Y2 JPH0236280 Y2 JP H0236280Y2 JP 1983033581 U JP1983033581 U JP 1983033581U JP 3358183 U JP3358183 U JP 3358183U JP H0236280 Y2 JPH0236280 Y2 JP H0236280Y2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- circuit board
- hybrid integrated
- integrated circuit
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 23
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 229920002050 silicone resin Polymers 0.000 claims description 8
- 229920003002 synthetic resin Polymers 0.000 claims description 4
- 239000000057 synthetic resin Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004570 mortar (masonry) Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000007115 recruitment Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000009974 thixotropic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
【考案の詳細な説明】
〔考案の技術分野〕
この考案は、半導体素子を回路基板にフリツプ
チツプボンデイングした混成集積回路装置に関す
る。[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a hybrid integrated circuit device in which a semiconductor element is flip-chip bonded to a circuit board.
半導体素子のフリツプチツプボンデイングは、
バンプと称されて導電金属(一般的にははんだ
材)で形成された突起電極を、半導体素子の電極
面に設け、このバンプ側を下向きにし回路基板上
の電極にはんだ接合している。このフリツプチツ
プボンデイングは、他の受動部品と同時にリフロ
ーはんだ付けができ、しかもボンデイング強度の
信頼性が高いので、広範囲の分野の電子部品に用
いられている。しかし、リードを有するデイスク
リート部品と異なり、半導体素子が裸であり、外
力に対して弱い欠点がある。
Flip-chip bonding of semiconductor devices is
A protruding electrode called a bump and made of a conductive metal (generally a solder material) is provided on the electrode surface of the semiconductor element, and the bump is soldered to the electrode on the circuit board with the bump side facing downward. This flip-chip bonding allows reflow soldering at the same time as other passive components and has high reliability in bonding strength, so it is used for electronic components in a wide range of fields. However, unlike discrete components with leads, the semiconductor element is bare and has the disadvantage of being vulnerable to external forces.
混成集積回路規模が次第に複雑化、システム化
していくと、できるだけ高密度で高集積化された
混成集積回路装置が要望されているが、フリツプ
チツプボンデイングでは上記のように取扱上の欠
点があるので、採用が制約されていた。 As the scale of hybrid integrated circuits becomes increasingly complex and systemized, there is a demand for hybrid integrated circuit devices that are as dense and highly integrated as possible, but flip-chip bonding has the disadvantages of handling as described above. Therefore, recruitment was restricted.
混成集積回路装置は高性能化され、回路規模が
大きくなり、高密度、高集積度にされてきてい
る。このため、半導体素子がフリツプチツプボン
デイングされた回路基板を、さらに、別のプリン
ト基板などへ取付けることが多くなつている。 Hybrid integrated circuit devices are becoming more sophisticated, have larger circuit scales, and are becoming more dense and highly integrated. For this reason, circuit boards on which semiconductor elements are flip-chip bonded are often further attached to other printed circuit boards.
この種の従来の高密度実装の混成集積回路装置
を、第1図に概要断面図で示す。1は混成集積回
路装置で、次のように構成されている。2は回路
基板、3はこの回路基板2上の配線導体(図示は
略す)上にフリツプチツプボンデイングされた半
導体素子、4は回路基板2上の配線導体にはんだ
付けされた各種の受動部品、5は回路基板2から
引出されたクリツプリードである。 A conventional high-density packaging hybrid integrated circuit device of this type is shown in a schematic cross-sectional view in FIG. 1 is a hybrid integrated circuit device, which is configured as follows. 2 is a circuit board; 3 is a semiconductor element flip-chip bonded on a wiring conductor (not shown) on the circuit board 2; 4 is various passive components soldered to the wiring conductor on the circuit board 2; 5 is a clip lead drawn out from the circuit board 2.
6はプリント基板(一般にマザーボードと称さ
れる)で、混成集積回路装置1、リード7を有す
る各種のデイスクリート部品8、IC9などを組
込んでいる。 Reference numeral 6 denotes a printed circuit board (generally referred to as a motherboard) in which a hybrid integrated circuit device 1, various discrete components 8 having leads 7, an IC 9, etc. are incorporated.
上記従来の装置では、回路基板1上の半導体素
子2が露出しており、機械的外力などにより割れ
たり、欠損したりし、不良が生じ信頼性が低かつ
た。これに対処し、混成集積回路装置1全体をエ
ポキシ樹脂などの熱硬化樹脂で樹脂封止したもの
にすると、半導体素子3と回路基板2とのわずか
のすき間に充てん樹脂が入り込み、熱硬化によ
り、双方の膨張係数など物理的性質の相違から、
応力が半導体素子3に加わり、ボンデイング部の
接着不良を生じ、信頼性を低下させるおそれがあ
る。 In the above-mentioned conventional device, the semiconductor element 2 on the circuit board 1 is exposed and can be cracked or chipped due to external mechanical force, resulting in defects and low reliability. To deal with this, if the entire hybrid integrated circuit device 1 is sealed with a thermosetting resin such as epoxy resin, the filling resin will enter the slight gap between the semiconductor element 3 and the circuit board 2, and due to thermosetting, Due to differences in physical properties such as expansion coefficients,
Stress is applied to the semiconductor element 3, resulting in poor adhesion at the bonding portion, which may reduce reliability.
これをなくするため、あらかじめ、混成集積回
路装置1を絶縁容器に収容し、充てんしたゲル状
シリコン樹脂により封止した装置があるが、作業
が面倒であり、また、占有容積が大きくなり、高
密度化実装を阻害していた。 In order to eliminate this problem, there is a device in which the hybrid integrated circuit device 1 is housed in an insulating container in advance and sealed with gel-like silicone resin, but this is cumbersome, takes up a large amount of space, and is expensive. This was hindering high-density implementation.
この考案は、回路基板上にフリツプチツプボン
デイングされた半導体素子の外周を、間隔をあけ
てキヤツプで囲い、このキヤツプは合成樹脂材か
らなり回路基板上に接着しており、囲い体の上部
に設けた注入穴から内部に注入したシリコン樹脂
により半導体素子を覆い、ゲル状にして封止し、
外部から保護し、封止作業が容易で簡単に行な
え、ボンデイングの信頼性が向上され、また、回
路装置の外形が増大せず、高密度実装に支障のな
いようにした、混成集積回路装置を提供すること
を目的としている。
In this idea, the outer periphery of a semiconductor element flip-chip bonded on a circuit board is surrounded by caps at intervals, and these caps are made of synthetic resin and are glued onto the circuit board. The silicone resin injected into the interior through the injection hole provided covers the semiconductor element and seals it in a gel state.
A hybrid integrated circuit device that is protected from the outside, can be easily sealed, has improved bonding reliability, does not increase the external size of the circuit device, and does not hinder high-density packaging. is intended to provide.
第2図はこの考案の一実施例による混成集積回
路装置の要部を示す断面図である。10は混成集
積回路装置で、上面に配線導体(図示は略す)が
形成された回路基板2上に半導体素子3がフリツ
プチツプボンデイングされ、受動部品4がはんだ
付けされてある。11は合成樹脂材からなり、半
導体素子3を間隔をあけて囲うすり鉢状のキヤツ
プで、上部に注入穴12があけられてあり、回路
基板2上に接着剤13で接着されている。この接
着剤13はシリコン系で硬化の早い樹脂を用い
る。14は注入器などにより注入穴12からキヤ
ツプ11内に注入され、半導体素子3を覆い、ゲ
ル化されたシリコン樹脂である。このゲル状シリ
コン樹脂14は、チクソ性のあるものを用いる
と、作業が容易である。
FIG. 2 is a sectional view showing the main parts of a hybrid integrated circuit device according to an embodiment of this invention. Reference numeral 10 designates a hybrid integrated circuit device, in which a semiconductor element 3 is flip-chip bonded onto a circuit board 2 on which wiring conductors (not shown) are formed, and passive components 4 are soldered. Reference numeral 11 denotes a mortar-shaped cap made of a synthetic resin material that surrounds the semiconductor element 3 at intervals, has an injection hole 12 in its upper part, and is bonded onto the circuit board 2 with an adhesive 13. This adhesive 13 uses a silicone-based resin that hardens quickly. A silicone resin 14 is injected into the cap 11 from the injection hole 12 using a syringe or the like, covers the semiconductor element 3, and is gelled. This gel-like silicone resin 14 can be easily worked if it has thixotropic properties.
このように、半導体素子3をゲル状シリコン樹
脂14で封じた混成集積回路装置10は、取扱い
が容易となる。 In this way, the hybrid integrated circuit device 10 in which the semiconductor element 3 is sealed with the gel-like silicone resin 14 is easy to handle.
なお、上記実施例では、キヤツプ11はすり鉢
状をなしているが、半導体素子3の側周及び上方
を間隔をあけて囲い上部に注入穴を設けたもので
あれば、半球状、あるいは上板のある円筒状な
ど、種々の形状のものであつてもよい。 In the above embodiment, the cap 11 is shaped like a mortar, but it can be shaped like a hemisphere or an upper plate if the cap 11 has an injection hole in the upper part and surrounds the semiconductor element 3 at a distance from the side periphery and above. It may be of various shapes, such as a circular cylindrical shape.
以上のように、考案によれば、回路基板上にフ
リツプチツプボンデイングされた半導体素子の外
周を間隔をあけ、合成樹脂材からなり上部に注入
穴があけられたキヤツプで囲い、このキヤツプを
回路基板上に接着し、上記注入穴からキヤツプ内
にシリコン樹脂を注入し、半導体素子を覆いゲル
状にして封じたので、封止作業が容易で簡単にで
き、半導体素子が外部から保護され、ボンデイン
グ部の信頼性が向上され、回路装置の外形が増大
することなく、プリント基板などへの組込みに、
高密度実装ができる。
As described above, according to the invention, the outer periphery of a semiconductor element flip-chip bonded on a circuit board is surrounded by a cap made of synthetic resin with an injection hole in the upper part, and this cap is used as a circuit board. It is adhered to the substrate, and silicone resin is injected into the cap through the injection hole, covering the semiconductor element and sealing it in a gel-like state, making the sealing process easy and simple, protecting the semiconductor element from the outside and preventing bonding. The reliability of the circuit has been improved, and it can be incorporated into printed circuit boards without increasing the external size of the circuit device.
High-density mounting is possible.
第1図は従来の混成集積回路装置を実装した状
態を示す概要断面図、第2図はこの考案の一実施
例による混成集積回路装置の要部を示す断面図で
ある。
図において、2……回路基板、3……半導体素
子、4……受動部品、10……混成集積回路装
置、11……キヤツプ、12……注入穴、13…
…接着剤、14……ゲル状シリコン樹脂。なお、
図中同一符号は同一又は相当部分を示す。
FIG. 1 is a schematic cross-sectional view showing a state in which a conventional hybrid integrated circuit device is mounted, and FIG. 2 is a cross-sectional view showing essential parts of a hybrid integrated circuit device according to an embodiment of the present invention. In the figure, 2... circuit board, 3... semiconductor element, 4... passive component, 10... hybrid integrated circuit device, 11... cap, 12... injection hole, 13...
...adhesive, 14...gel silicone resin. In addition,
The same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
た半導体素子、合成樹脂材からなり上部に注入穴
があけられてあり、上記半導体素子を間隔をあけ
て囲い上記回路基板上に接着されたキヤツプ、及
び上記注入穴から上記キヤツプ内に注入されて上
記半導体素子を覆い、ゲル状にされ封止したシリ
コン樹脂を備えた混成集積回路装置。 A semiconductor element flip-chip bonded on a circuit board, a cap made of a synthetic resin material and having an injection hole in its upper part, surrounding the semiconductor element at intervals and bonded to the circuit board, A hybrid integrated circuit device comprising a silicone resin injected into the cap through the hole to cover the semiconductor element, gelled and sealed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983033581U JPS59138236U (en) | 1983-03-07 | 1983-03-07 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983033581U JPS59138236U (en) | 1983-03-07 | 1983-03-07 | Hybrid integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59138236U JPS59138236U (en) | 1984-09-14 |
JPH0236280Y2 true JPH0236280Y2 (en) | 1990-10-03 |
Family
ID=30164364
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1983033581U Granted JPS59138236U (en) | 1983-03-07 | 1983-03-07 | Hybrid integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59138236U (en) |
-
1983
- 1983-03-07 JP JP1983033581U patent/JPS59138236U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS59138236U (en) | 1984-09-14 |
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