JPH023542B2 - - Google Patents
Info
- Publication number
- JPH023542B2 JPH023542B2 JP11220682A JP11220682A JPH023542B2 JP H023542 B2 JPH023542 B2 JP H023542B2 JP 11220682 A JP11220682 A JP 11220682A JP 11220682 A JP11220682 A JP 11220682A JP H023542 B2 JPH023542 B2 JP H023542B2
- Authority
- JP
- Japan
- Prior art keywords
- charge transfer
- charge
- output gate
- transfer device
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 239000000969 carrier Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76816—Output structures
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
【発明の詳細な説明】
本発明は電荷結合装置に関し、特に2本の電荷
結合素子の出力を交互に取り出すことが出来る電
荷転送装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge coupled device, and more particularly to a charge transfer device that can alternately take out the outputs of two charge coupled devices.
第1図は従来の電荷転送装置の一例を示す図
で、転送電極及び出力ゲート電極の配列を示す平
面図に説明の都合上電荷検出装置の回路接続図を
書き入れてある。この電荷転送装置は、半導体基
板1の表面上に酸化膜を介して連続して配列され
た複数の電荷転送電極2,3,4,5,2′,
3′,4′,5′に転送用電圧として第2図に示す
ようなタイミングでクロツクψ1,ψ2,ψ3,ψ4を
加えることにより、これら転送電極下に形成され
る電荷転送チヤネルを用いて電荷の転送を行なう
ものである。第1図に示す電荷転送装置は表面チ
ヤネル型電荷結合装置を例にしたものであるが、
説明を簡単化するため電荷転送装置は表面チヤネ
ルCCDとし、半導体基板はP型とし、転送され
る電荷、即ちキヤリアは電子とする。 FIG. 1 is a diagram showing an example of a conventional charge transfer device, in which a circuit connection diagram of a charge detection device is included for convenience of explanation in a plan view showing the arrangement of transfer electrodes and output gate electrodes. This charge transfer device includes a plurality of charge transfer electrodes 2, 3, 4, 5, 2', which are continuously arranged on the surface of a semiconductor substrate 1 with an oxide film interposed therebetween.
By applying clocks ψ 1 , ψ 2 , ψ 3 , ψ 4 as transfer voltages to 3', 4', and 5' at the timing shown in Figure 2, a charge transfer channel is formed under these transfer electrodes. This is used to transfer charges. The charge transfer device shown in FIG. 1 is an example of a surface channel charge coupled device.
To simplify the explanation, it is assumed that the charge transfer device is a surface channel CCD, that the semiconductor substrate is of P type, and that the charges to be transferred, that is, carriers, are electrons.
ここで第1図において、1はP型半導体基板、
2〜5,2′〜5′は転送用ゲート電極、6は出力
ゲート電極、11はP型半導体基板に設けられた
N型拡散層であり、転送されて来る電荷を検出す
る電荷検出用領域である。第1図、第2図を用
い、この検出部の動作を説明する。 Here, in FIG. 1, 1 is a P-type semiconductor substrate;
2 to 5, 2' to 5' are transfer gate electrodes, 6 is an output gate electrode, and 11 is an N type diffusion layer provided on a P type semiconductor substrate, which is a charge detection area for detecting transferred charges. It is. The operation of this detection section will be explained using FIGS. 1 and 2.
時刻t1においてψRに「高」レベルを加え、
MOSTr1を導通させ、そのソース電位VS1をTr1
のドレイン電位VRDと同電位に設定する。時刻t2
にψRは「低」レベルとし、ソース領域11はフ
ローテイング状態となる。この状態後に時刻t3に
おいてψ4を「低」レベルにし電極5の下に蓄積
されていたキヤリアを一定電位VOGが加えられて
いる出力ゲート電極6の下のチヤネルを通し、ソ
ース領域11に流入させる。この流入電荷による
VS1の電位変化をMOSトランジスタTr2と抵抗R1
よりなるソースフオロワー回路のMOSトランジ
スタTr2のゲートに加えることにより、出力信号
をVput端子9より取り出される。また時刻t4,t5,
t6の経過にともない、同様にしてψ2ゲード3′に
蓄積された電荷を電圧に変換して出力信号として
Vput端子より取り出す。 Add a “high” level to ψ R at time t 1 ,
MOSTr 1 is made conductive and its source potential V S1 becomes T r1
Set to the same potential as the drain potential V RD of . time t 2
In this case, ψ R is set to a "low" level, and the source region 11 is in a floating state. After this state, at time t 3 ψ 4 is set to a “low” level, and the carriers accumulated under the electrode 5 are passed through the channel under the output gate electrode 6 to which a constant potential V OG is applied, and are transferred to the source region 11. Let it flow. Due to this inflow charge
The change in potential of V S1 is expressed by MOS transistor T r2 and resistor R 1.
The output signal is taken out from the V put terminal 9 by applying it to the gate of the MOS transistor T r2 of the source follower circuit. Also, at times t 4 , t 5 ,
As t 6 elapses, the charge accumulated in ψ 2 gate 3' is similarly converted to voltage and output as an output signal.
Take it out from the V put terminal.
このようにして二系列の電荷転送素子の出力は
交互に取り出されるのであるが、従来の第1図に
示すような出力ゲート端子への配線では以下に述
べる欠点があつた。 In this way, the outputs of the two series of charge transfer elements are taken out alternately, but the conventional wiring to the output gate terminal as shown in FIG. 1 has the following drawbacks.
電荷転送用電極、及び出力ゲート電極は、お互
いに電荷転送効率の劣化を防止するために、重ね
合わせ構造をとつている。ところが、この重ね合
わせ構造のため、各電極間に大きなカツプリング
容量が存在する。このカツプリング容量の存在の
ためψ4及びψ2クロツクが変化する時、出力ゲー
ト電位も変動を受ける。特に出力ゲートが多結晶
Siで作製されている場合、VOG端子より、出力ゲ
ート先端までの抵抗は大きなものとなるため、こ
の出力ゲート電位の変動は大きなものとなる。こ
の出力ゲート電位の変動は(1)出力ゲート下のチヤ
ネルポテンシヤルの変動をもたらし、出力ゲート
下の電荷転送スピードに影響を与える、(2)出力ゲ
ートと電荷検出領域とのカツプリング容量の存在
のため、出力ゲート電位の変動は高入力インピー
ダンスの電荷検出領域の電位変動となり、電荷検
出部のS/N比の低下をひき起こす。 The charge transfer electrode and the output gate electrode have an overlapping structure in order to prevent deterioration of charge transfer efficiency with each other. However, due to this stacked structure, a large coupling capacitance exists between each electrode. Due to the presence of this coupling capacitance, when the ψ 4 and ψ 2 clocks change, the output gate potential also undergoes fluctuations. Especially the output gate is polycrystalline.
If it is made of Si, the resistance from the V OG terminal to the tip of the output gate will be large, so the fluctuation in the output gate potential will be large. This variation in output gate potential (1) causes a variation in the channel potential under the output gate, which affects the charge transfer speed under the output gate, and (2) due to the presence of coupling capacitance between the output gate and the charge detection region. , fluctuations in the output gate potential result in potential fluctuations in the charge detection region with high input impedance, causing a decrease in the S/N ratio of the charge detection section.
以上述べたことを第3図a、第4図を用い具体
的に説明する。第3図aは、VOG端子より見たと
ころの従来配線での分布定数的に表現した等価回
路である。ここでC1 4−OG,C2 4−OG,C3 4−OGは出力
ゲート電極とψ4ゲートとのカツプリング容量、
C1 2−OG,C2 2−OG,C3 2−OGは出力ゲート電極とψ2ゲ
ートとのカツプリング容量、COGは出力ゲート電
極と基板との容量、ROGは出力ゲート電極の抵抗
である。但し、簡単のため分布定数は一定とし
た。ここでいま第4図に示すようなクロツク波形
をψ4,ψ2端子に加えた場合、カツプリング容量
とROG抵抗のため出力ゲート部の等価回路内の
VOG−4の節点とVOG−2の節点とには第4図に示す
ようなスパイク状の雑音が混入する。この種の雑
音は第4図でわかるようにVOG−4の節点とVOG−2
の節点で大きさが違うとともに、ψ4端子のクロ
ツク波形の立下りとψ2端子のクロツク波形の立
上りのタイミングに違いがあると一層、顕著に現
われる。従つて第4図に示すように、出力端子
Vputには雑音成分が存在してしまう。 The above description will be specifically explained using FIGS. 3a and 4. FIG. 3a is an equivalent circuit expressed in terms of distributed constants with conventional wiring as seen from the VOG terminal. Here, C 1 4 − OG , C 2 4 − OG , C 3 4 − OG are the coupling capacitances between the output gate electrode and the ψ 4 gate,
C 1 2 − OG , C 2 2 − OG , C 3 2 − OG is the coupling capacitance between the output gate electrode and the ψ 2 gate, C OG is the capacitance between the output gate electrode and the substrate, and R OG is the resistance of the output gate electrode. It is. However, for simplicity, the distribution constant was assumed to be constant. Now, if a clock waveform as shown in Fig. 4 is applied to the ψ 4 and ψ 2 terminals, the output gate part's equivalent circuit will change due to the coupling capacitance and ROG resistance.
Spike-like noise as shown in FIG. 4 is mixed into the nodes of V OG - 4 and V OG - 2 . This type of noise can be seen at the nodes of V OG − 4 and V OG − 2 , as shown in Figure 4.
This becomes even more noticeable when there is a difference in size at the nodes, and there is also a difference in timing between the falling edge of the clock waveform at the ψ4 terminal and the rising edge of the clock waveform at the ψ2 terminal. Therefore, as shown in Figure 4, the output terminal
Noise components exist in V put .
本発明はこのような欠点がなく、信号対雑音比
の改善された電荷転送素子を提供することを目的
とする。 It is an object of the present invention to provide a charge transfer device that is free from such drawbacks and has an improved signal-to-noise ratio.
本発明によれば、一導電型半導体基板上に絶縁
膜を介して設けられた転送電極をもつ電荷転送素
子と、同じく絶縁膜を介して設けられた出力ゲー
ト電極と、転送電荷を検出する電荷検出装置とを
含み、前記二系列の電荷転送素子の出力を交互に
取り出す手段を備えた電荷転送装置において、前
記出力ゲート電極の中央部に特別に、カツプリン
グ容量C1 4−OG,C2 4−OG,C3 4−OG,C1 2−OG,C2 2−OG
,
C3 2−OGの総合計した容量に対し少なくとも100倍
以上の特別に設けた容量COGLを付加したことを特
徴とする電荷転送装置が得られ、結果として、出
力ゲート電極の中央部に特別に設けられた容量
COGLによつて、過渡性雑音は、完全に無視できる
まで小さくなり、出力信号に表われる雑音成分を
消滅させる効果がある。 According to the present invention, there is provided a charge transfer element having a transfer electrode provided on a semiconductor substrate of one conductivity type via an insulating film, an output gate electrode also provided via an insulating film, and a charge transfer element for detecting transferred charges. In the charge transfer device including a detection device and means for alternately extracting the outputs of the two series of charge transfer elements, coupling capacitors C 1 4 − OG , C 2 4 are specially provided at the center of the output gate electrode. − OG , C 3 4 − OG , C 1 2 − OG , C 2 2 − OG
,
A charge transfer device is obtained in which a specially provided capacitance C OGL is added which is at least 100 times the total capacitance of C 3 2 − OG . capacity provided for
C OGL reduces transient noise to the point where it can be completely ignored, and has the effect of eliminating noise components appearing in the output signal.
なお、電荷転送装置の構造は表面チヤネル型電
荷結合形に限られるものではなく、装置の一部、
あるいは全ての部分が押込みチヤネルあるいはバ
ケツトブリゲード素子の形であつても良い。また
基板はP型に限つたものではなく、導電型の極性
を逆にし、少数キヤリアを正孔とすれば基板がN
型であつてもよいことはいうまでもない。 Note that the structure of the charge transfer device is not limited to the surface channel charge-coupled type;
Alternatively, all parts may be in the form of push-in channels or bucket brigade elements. Also, the substrate is not limited to P-type, but if the polarity of the conductivity type is reversed and the minority carriers are holes, the substrate becomes N-type.
It goes without saying that it may be a type.
第5図は本発明の一実施例を示す図で、転送電
極及び出力ゲート電極の配置を示す平面図に説明
の都合上、電荷検出装置の回路図を書き入れてあ
る。なお、第5図の14が本発明にかかる特別に
設けられた容量である。 FIG. 5 is a diagram showing an embodiment of the present invention, in which a circuit diagram of a charge detection device is included for convenience of explanation in a plan view showing the arrangement of transfer electrodes and output gate electrodes. Note that 14 in FIG. 5 is a specially provided capacitor according to the present invention.
第1図は重ね合わせ電極構造をもつた従来の電
荷結合装置を示す図、第2図は電荷結合装置を駆
動する入力パルスの一例を示すグラフ、第3図a
はVOG端子より見たところの従来例の等価回路、
第3図bはVOG端子より見たところの本発明電荷
転送装置の等価回路、第4図はクロツクパルスが
出力ゲート電位および信号出力に与える影響を説
明するための図、第5図は本発明の一実施例を示
す図、である。
なお図において、1……P型半導体基板、2,
3,4,5,2′,3′,4′,5′……転送電極、
6,6′……出力ゲート電極、7……VRD端子、
8……VOD端子、9……出力端子、10……抵
抗、11,11′,11″……電荷検出用拡散層、
12,13……MOSトランジスタ、14……容
量、15……雑音成分、である。
FIG. 1 is a diagram showing a conventional charge-coupled device with an overlapping electrode structure, FIG. 2 is a graph showing an example of an input pulse for driving a charge-coupled device, and FIG. 3a
is the equivalent circuit of the conventional example as seen from the V OG terminal,
Fig. 3b is an equivalent circuit of the charge transfer device of the present invention as seen from the V OG terminal, Fig. 4 is a diagram for explaining the influence of the clock pulse on the output gate potential and signal output, and Fig. 5 is the equivalent circuit of the charge transfer device of the present invention as seen from the V OG terminal. FIG. 2 is a diagram showing an example. In the figure, 1...P-type semiconductor substrate, 2,
3, 4, 5, 2', 3', 4', 5'...transfer electrode,
6, 6'...Output gate electrode, 7...V RD terminal,
8...V OD terminal, 9...Output terminal, 10...Resistor, 11, 11', 11''...Diffusion layer for charge detection,
12, 13...MOS transistor, 14...capacitance, 15...noise component.
Claims (1)
られた転送電極をもつ二系列の電荷転送素子と、
該絶縁膜を介して設けられた出力ゲート電極と転
送電荷を検出する電荷検出装置とを含み、前記二
系列の電荷転送素子の出力を交互に取り出す手段
を備えた電荷転送装置において、前記出力ゲート
電極の中間点に容量を負荷したことを特徴とする
電荷転送装置。1. Two series of charge transfer elements having transfer electrodes provided on one conductivity type semiconductor substrate with an insulating film interposed therebetween;
In the charge transfer device, the charge transfer device includes an output gate electrode provided through the insulating film and a charge detection device for detecting transferred charges, and includes means for alternately extracting outputs of the two series of charge transfer elements. A charge transfer device characterized in that a capacitance is loaded at a midpoint between electrodes.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11220682A JPS593972A (en) | 1982-06-29 | 1982-06-29 | Charge transfer device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11220682A JPS593972A (en) | 1982-06-29 | 1982-06-29 | Charge transfer device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS593972A JPS593972A (en) | 1984-01-10 |
JPH023542B2 true JPH023542B2 (en) | 1990-01-24 |
Family
ID=14580904
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11220682A Granted JPS593972A (en) | 1982-06-29 | 1982-06-29 | Charge transfer device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS593972A (en) |
-
1982
- 1982-06-29 JP JP11220682A patent/JPS593972A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS593972A (en) | 1984-01-10 |
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