JPH023542B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge coupled device, and more particularly to a charge transfer device that can alternately take out the outputs of two charge coupled devices.

FIG. 1 is a diagram showing an example of a conventional charge transfer device, in which a circuit connection diagram of a charge detection device is included for convenience of explanation in a plan view showing the arrangement of transfer electrodes and output gate electrodes. This charge transfer device includes a plurality of charge transfer electrodes 2, 3, 4, 5, 2', which are continuously arranged on the surface of a semiconductor substrate 1 with an oxide film interposed therebetween.
By applying clocks ψ ₁ , ψ ₂ , ψ ₃ , ψ ₄ as transfer voltages to 3', 4', and 5' at the timing shown in Figure 2, a charge transfer channel is formed under these transfer electrodes. This is used to transfer charges. The charge transfer device shown in FIG. 1 is an example of a surface channel charge coupled device.
To simplify the explanation, it is assumed that the charge transfer device is a surface channel CCD, that the semiconductor substrate is of P type, and that the charges to be transferred, that is, carriers, are electrons.

Here, in FIG. 1, 1 is a P-type semiconductor substrate;
2 to 5, 2' to 5' are transfer gate electrodes, 6 is an output gate electrode, and 11 is an N type diffusion layer provided on a P type semiconductor substrate, which is a charge detection area for detecting transferred charges. It is. The operation of this detection section will be explained using FIGS. 1 and 2.

Add a “high” level to ψ _R at time t ₁ ,
MOSTr ₁ is made conductive and its source potential V _S1 becomes T _r1
Set to the same potential as the drain potential V _RD of . time t ₂
In this case, ψ _R is set to a "low" level, and the source region 11 is in a floating state. After this state, at time t ₃ ψ ₄ is set to a “low” level, and the carriers accumulated under the electrode 5 are passed through the channel under the output gate electrode 6 to which a constant potential V _OG is applied, and are transferred to the source region 11. Let it flow. Due to this inflow charge
The change in potential of V _S1 is expressed by MOS transistor T _r2 and resistor R _1.
The output signal is taken out from the V _put terminal 9 by applying it to the gate of the MOS transistor T _r2 of the source follower circuit. Also, at times t ₄ , t ₅ ,
As t ₆ elapses, the charge accumulated in ψ ₂ gate 3' is similarly converted to voltage and output as an output signal.
Take it out from the V _put terminal.

In this way, the outputs of the two series of charge transfer elements are taken out alternately, but the conventional wiring to the output gate terminal as shown in FIG. 1 has the following drawbacks.

The charge transfer electrode and the output gate electrode have an overlapping structure in order to prevent deterioration of charge transfer efficiency with each other. However, due to this stacked structure, a large coupling capacitance exists between each electrode. Due to the presence of this coupling capacitance, when the ψ ₄ and ψ ₂ clocks change, the output gate potential also undergoes fluctuations. Especially the output gate is polycrystalline.
If it is made of Si, the resistance from the V _OG terminal to the tip of the output gate will be large, so the fluctuation in the output gate potential will be large. This variation in output gate potential (1) causes a variation in the channel potential under the output gate, which affects the charge transfer speed under the output gate, and (2) due to the presence of coupling capacitance between the output gate and the charge detection region. , fluctuations in the output gate potential result in potential fluctuations in the charge detection region with high input impedance, causing a decrease in the S/N ratio of the charge detection section.

The above description will be specifically explained using FIGS. 3a and 4. FIG. 3a is an equivalent circuit expressed in terms of distributed constants with conventional wiring as seen from the _VOG terminal. Here, C ¹ ₄ − _OG , C ² ₄ − _OG , C ³ ₄ − _OG are the coupling capacitances between the output gate electrode and the ψ ₄ gate,
C ¹ ₂ − _OG , C ² ₂ − _OG , C ³ ₂ − _OG is the coupling capacitance between the output gate electrode and the ψ ₂ gate, C _OG is the capacitance between the output gate electrode and the substrate, and R _OG is the resistance of the output gate electrode. It is. However, for simplicity, the distribution constant was assumed to be constant. Now, if a clock waveform as shown in Fig. 4 is applied to the ψ ₄ and ψ ₂ terminals, the output gate part's equivalent circuit will change due to the coupling capacitance and _ROG resistance.
Spike-like noise as shown in FIG. 4 is mixed into the nodes of V _OG - ₄ and V _OG - ₂ . This type of noise can be seen at the nodes of V _OG − ₄ and V _OG − ₂ , as shown in Figure 4.
This becomes even more noticeable when there is a difference in size at the nodes, and there is also a difference in timing between the falling edge of the clock waveform at the _ψ4 terminal and the rising edge of the clock waveform at the _ψ2 terminal. Therefore, as shown in Figure 4, the output terminal
Noise components exist in V _put .

It is an object of the present invention to provide a charge transfer device that is free from such drawbacks and has an improved signal-to-noise ratio.

According to the present invention, there is provided a charge transfer element having a transfer electrode provided on a semiconductor substrate of one conductivity type via an insulating film, an output gate electrode also provided via an insulating film, and a charge transfer element for detecting transferred charges. In the charge transfer device including a detection device and means for alternately extracting the outputs of the two series of charge transfer elements, coupling capacitors C ¹ ₄ − _OG , C ² ₄ are specially provided at the center of the output gate electrode. − _OG , C ³ ₄ − _OG , C ¹ ₂ − _OG , C ² ₂ − _OG
，
A charge transfer device is obtained in which a specially provided capacitance C _OGL is added which is at least 100 times the total capacitance of C ³ ₂ − _OG . capacity provided for
C _OGL reduces transient noise to the point where it can be completely ignored, and has the effect of eliminating noise components appearing in the output signal.

Note that the structure of the charge transfer device is not limited to the surface channel charge-coupled type;
Alternatively, all parts may be in the form of push-in channels or bucket brigade elements. Also, the substrate is not limited to P-type, but if the polarity of the conductivity type is reversed and the minority carriers are holes, the substrate becomes N-type.
It goes without saying that it may be a type.

FIG. 5 is a diagram showing an embodiment of the present invention, in which a circuit diagram of a charge detection device is included for convenience of explanation in a plan view showing the arrangement of transfer electrodes and output gate electrodes. Note that 14 in FIG. 5 is a specially provided capacitor according to the present invention.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional charge-coupled device with an overlapping electrode structure, FIG. 2 is a graph showing an example of an input pulse for driving a charge-coupled device, and FIG. 3a
is the equivalent circuit of the conventional example as seen from the V _OG terminal,
Fig. 3b is an equivalent circuit of the charge transfer device of the present invention as seen from the V _OG terminal, Fig. 4 is a diagram for explaining the influence of the clock pulse on the output gate potential and signal output, and Fig. 5 is the equivalent circuit of the charge transfer device of the present invention as seen from the V OG terminal. FIG. 2 is a diagram showing an example. In the figure, 1...P-type semiconductor substrate, 2,
3, 4, 5, 2', 3', 4', 5'...transfer electrode,
6, 6'...Output gate electrode, 7...V _RD terminal,
8...V _OD terminal, 9...Output terminal, 10...Resistor, 11, 11', 11''...Diffusion layer for charge detection,
12, 13...MOS transistor, 14...capacitance, 15...noise component.

Claims (1)

[Claims] 1. Two series of charge transfer elements having transfer electrodes provided on one conductivity type semiconductor substrate with an insulating film interposed therebetween;
In the charge transfer device, the charge transfer device includes an output gate electrode provided through the insulating film and a charge detection device for detecting transferred charges, and includes means for alternately extracting outputs of the two series of charge transfer elements. A charge transfer device characterized in that a capacitance is loaded at a midpoint between electrodes.